公开(公告)号：US07865650B2

公开(公告)日：2011-01-04

申请号：US12060670

申请日：2008-04-01

申请人： Charles Francis Marino ,  John Thomas Holloway, Jr. ,  Praveen S Reddy ,  William John Starke

发明人： Charles Francis Marino ,  John Thomas Holloway, Jr. ,  Praveen S Reddy ,  William John Starke

IPC分类号： G06F13/14

CPC分类号： H01L27/0207 ,  H01L27/11898

摘要： A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of the processor chip. The I/O interfaces may be distributed uniformly along portions of the perimeter.

摘要翻译： 对称多处理（SMP）处理器包括用于在沿着主互连干线位于多个计算单元之间进行信息通信的主互连干线。 处理器还包括可相对于主互连干线垂直定向的次级互连干线。 辅助互连中继线通过处理器芯片周边的多个I / O接口来传送芯片外的信息。 I / O接口可以沿周边的部分均匀分布。

公开(公告)号：US20100268887A1

公开(公告)日：2010-10-21

申请号：US12424255

申请日：2009-04-15

申请人： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke

发明人： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0811

摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.

摘要翻译： 信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。 处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。 处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。 仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。 缓存系统向数据流提供双调度点到二级高速缓冲存储器的双缓存组。

公开(公告)号：US20100268882A1

公开(公告)日：2010-10-21

申请号：US12424207

申请日：2009-04-15

申请人： Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  Stephen James Powell ,  William John Starke ,  Jeffrey A. Stuecheli

发明人： Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  Stephen James Powell ,  William John Starke ,  Jeffrey A. Stuecheli

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/123 ,  G06F12/084 ,  G06F12/0897

摘要： A system and method for tracking core load requests and providing arbitration and ordering of requests. When a core interface unit (CIU) receives a load operation from the processor core, a new entry in allocated in a queue of the CIU. In response to allocating the new entry in the queue, the CIU detects contention between the load request and another memory access request. In response to detecting contention, the load request may be suspended until the contention is resolved. Received load requests may be stored in the queue and tracked using a least recently used (LRU) mechanism. The load request may then be processed when the load request resides in a least recently used entry in the load request queue. CIU may also suspend issuing an instruction unless a read claim (RC) machine is available. In another embodiment, CIU may issue stored load requests in a specific priority order.

摘要翻译： 用于跟踪核心负载请求并提供仲裁和请求排序的系统和方法。 当核心接口单元（CIU）从处理器核心接收到加载操作时，分配在CIU队列中的新条目。 响应于在队列中分配新条目，CIU检测加载请求和另一个存储器访问请求之间的争用。 响应于检测到争用，负载请求可以被暂停，直到争用被解决。 接收到的加载请求可以存储在队列中，并使用最近最少使用的（LRU）机制进行跟踪。 然后可以在加载请求驻留在加载请求队列中最近最少使用的条目中时处理加载请求。 除非读取权利要求（RC）机器可用，否则CIU也可以暂停发出指令。 在另一个实施例中，CIU可以以特定优先级顺序发布存储的加载请求。

公开(公告)号：US07783834B2

公开(公告)日：2010-08-24

申请号：US11947742

申请日：2007-11-29

申请人： Leo James Clark ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston ,  William John Starke

发明人： Leo James Clark ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston ,  William John Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0822 ,  G06F12/0824

摘要： A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency. One set of wires oriented along a horizontal direction may be used to output the cache line, while another set of wires oriented along a vertical direction may be used for maintenance of the cache sectors. A given cache line is further preferably spread across sectors in different rows or cache ways. For example, a cache line can be 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line, and the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.

摘要翻译： 缓存存储器逻辑地将高速缓存行与高速缓存阵列的至少两个缓存扇区相关联，其中不同扇区具有不同的输出延迟，并且对于负载命中，基于它们的等待时间来选择性地启用高速缓存扇区以在连续的时钟周期上输出高速缓存行 。 优选使用具有较高传输速度的较大导线来输出与所请求的存储块相对应的高速缓存行。 在说明性实施例中，高速缓存器配置有高速缓存扇区的行和列，并且给定的高速缓存行分布在不同列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列中 并且所述给定高速缓存行的另一部分位于具有大于所述第一等待时间的第二等待时间的第二列中。 可以使用沿水平方向定向的一组线来输出高速缓存线，而沿着垂直方向定向的另一组线可以用于高速缓存扇区的维护。 给定的高速缓存行进一步优选地分布在不同行或高速缓存方式的扇区之间。 例如，高速缓存行可以是128字节并且分布在四个不同列中的四个扇区上，每个扇区包含32个字节的高速缓存行，并且高速缓存行在四个连续的时钟周期内被输出，在每个 四个周期。

公开(公告)号：US20090248940A1

公开(公告)日：2009-10-01

申请号：US12060683

申请日：2008-04-01

申请人： Charles Francis Marino ,  John Thomas Hollaway, JR. ,  Praveen S. Reddy ,  William John Starke

发明人： Charles Francis Marino ,  John Thomas Hollaway, JR. ,  Praveen S. Reddy ,  William John Starke

IPC分类号： G06F13/14

CPC分类号： G06F15/8007

摘要： An integrated circuit (IC) processor chip apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. That multiple processor chip includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of that multiple processor chip. The I/O interfaces may be distributed uniformly along portions of the perimeter of that multiple processor chip.

摘要翻译： 集成电路（IC）处理器芯片装置在基板上包括多个处理器芯片。 多个处理器芯片中的至少一个包括具有主互连干线的管芯，用于在沿着主互连干线位于的多个计算元件之间进行信息通信。 该多处理器芯片包括可相对于主互连干线垂直定向的次级互连干线。 辅助互连中继线通过多处理器芯片周边的多个I / O接口来传送芯片外的信息。 I / O接口可以沿着该多处理器芯片的周边的一部分均匀地分布。

公开(公告)号：US07500065B2

公开(公告)日：2009-03-03

申请号：US11956102

申请日：2007-12-13

申请人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

发明人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

摘要翻译： 一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。 较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。 一致性状态表实现替换策略，其在从上部存储器高速缓存中拔出时，在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。

公开(公告)号：US20090024878A1

公开(公告)日：2009-01-22

申请号：US12201557

申请日：2008-08-29

申请人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

发明人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/2268 ,  G06F11/348

摘要： An apparatus and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.

摘要翻译： 公开了一种用于使用现有系统总线在处理器中执行存储器内硬件跟踪的装置和计算机程序产品。 处理器包括利用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控​​制器。 利用系统总线在处理单元之间传送信息。 信息根据标准系统总线协议进行格式化。 使用直接耦合到系统总线的硬件跟踪功能来捕获硬件跟踪数据。 系统总线用于将硬件跟踪数据发送到存储器控制器以存储在系统存储器中。 存储器控制器直接耦合到系统总线。 硬件跟踪数据根据标准系统总线协议进行格式化，以便通过系统总线进行传输。

公开(公告)号：US20090006825A1

公开(公告)日：2009-01-01

申请号：US12210005

申请日：2008-09-12

申请人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

发明人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

IPC分类号： G06F9/30

CPC分类号： G06F11/2268 ,  G06F11/348

摘要： A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.

摘要翻译： 公开了一种方法，装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。 硬件跟踪设备捕获处理器中的硬件跟踪数据。 硬件跟踪工具包含在处理器内。 使用系统总线将硬件跟踪数据传输到系统存储器。 系统内存包含在系统中。 当硬件跟踪数据被传送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。 系统内存的一部分用于存储跟踪数据。 系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。

公开(公告)号：US07337280B2

公开(公告)日：2008-02-26

申请号：US11055301

申请日：2005-02-10

申请人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

发明人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

摘要翻译： 一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。 较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。 一致性状态表实现替换策略，其在从上部存储器高速缓存中拔出时，在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。

公开(公告)号：US07200717B2

公开(公告)日：2007-04-03

申请号：US10965144

申请日：2004-10-14

申请人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3851 ,  G06F12/0855

摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit coupled to the instruction sequencing unit that concurrently executes multiple threads of instructions. The processor core, responsive to the at least one instruction execution unit executing a load-reserve instruction in a first thread that binds to a load target address in the store-through upper level cache during a reservation hazard window associated with a conflicting store-conditional operation of a second thread, causes a subsequent store-conditional operation of the first thread to a store target address matching the load target address to fail if the store-conditional operation of the second thread succeeds.

摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括处理器核心，该处理器核心包括通过存储的上级高速缓存，指令执行指令排序单元，数据寄存器以及耦合到指令排序单元的至少一个指令执行单元， 同时执行多个指令线程。 所述处理器核心响应于所述至少一个指令执行单元在与冲突存储条件相关联的预留危险窗口期间执行在所述存储通过上级高速缓存中的绑定到加载目标地址的第一线程中的加载保留指令 如果第二线程的存储条件操作成功，则第二线程的操作使得第一线程的后续存储条件操作到与加载目标地址匹配的存储目标地址失败。