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    Recessed gate transistor structure and method of forming the same
    101.
    发明授权
    Recessed gate transistor structure and method of forming the same 有权
    嵌入式晶体管结构及其形成方法

    公开(公告)号：US07777258B2

    公开(公告)日：2010-08-17

    申请号：US11560756

    申请日：2006-11-16

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L29/66621 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7834

    摘要： Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.

    摘要翻译： 嵌入栅极晶体管结构及其制造方法即使在形成栅极时产生不对准，也可以通过在其间形成绝缘层来防止形成在非有源区上的栅极导电层与有源区之间的短路。 该方法和结构降低了门之间的电容。 该方法包括在半导体衬底的预定区域上形成用于限定有源区和非有源区的器件隔离膜。 第一和第二绝缘层形成在基板的整个表面上。 在有源区域的一部分中形成凹部。 在凹部内形成栅极绝缘层，然后在凹部内形成第一栅极导电层。 第二栅极导电层形成在第二绝缘层和第一栅极导电层上。 随后，形成源/漏区。

    METHOD AND APPARATUS FOR PROVIDING AUTOMATIC INTERNATIONAL AND LOCAL CALL DIALING IN A MOBILE COMMUNICATION TERMINAL
    102.
    发明申请
    METHOD AND APPARATUS FOR PROVIDING AUTOMATIC INTERNATIONAL AND LOCAL CALL DIALING IN A MOBILE COMMUNICATION TERMINAL 有权
    在移动通信终端中提供自动国际和本地呼叫拨号的方法和装置

    公开(公告)号：US20100184413A1

    公开(公告)日：2010-07-22

    申请号：US12689886

    申请日：2010-01-19

    申请人： Sun-Haeng JO ,  Bo-Ram Park ,  Ji-Young Kim ,  Seong-Hoon Kang ,  Hye-Soo Lee

    发明人： Sun-Haeng JO ,  Bo-Ram Park ,  Ji-Young Kim ,  Seong-Hoon Kang ,  Hye-Soo Lee

    IPC分类号： H04M3/42

    CPC分类号： H04W8/02 ,  H04M1/274558 ,  H04M1/274566 ,  H04M15/00 ,  H04M15/80 ,  H04M2215/0152 ,  H04M2250/60 ,  H04W4/24

    摘要： A method and apparatus for providing automatic international and local call dialing in a mobile communication terminal. Country identification information is received from a network in which the mobile communication terminal is currently located. When a request for an outgoing is received from a user, a country code corresponding to the received country identification information is extracted, and the extracted country code is compared with a country code included in a phone number for the outgoing call. Based on the comparison it is determined whether the outgoing call is an international or local call. The phone number is then changed in accordance with the outgoing call being the international or local call.

    摘要翻译： 一种用于在移动通信终端中提供自动国际和本地呼叫拨号的方法和装置。 从移动通信终端当前所在的网络接收到国家识别信息。 当从用户接收到发出的请求时，提取与接收到的国家标识信息相对应的国家代码，并将所提取的国家代码与包括在呼出电话的电话号码中的国家代码进行比较。 基于比较，确定呼出呼叫是否是国际或本地呼叫。 然后根据作为国际或本地呼叫的呼出来更改电话号码。

    FILTER FOR DISPLAY DEVICE
    103.
    发明申请
    FILTER FOR DISPLAY DEVICE 审中-公开
    显示设备过滤器

    公开(公告)号：US20090128895A1

    公开(公告)日：2009-05-21

    申请号：US12274700

    申请日：2008-11-20

    申请人： Ji-Yoon Seo ,  Dong-Keun Sin ,  Sang-Yoon Oh ,  Dae Chul Park ,  Ji-Young Kim

    发明人： Ji-Yoon Seo ,  Dong-Keun Sin ,  Sang-Yoon Oh ,  Dae Chul Park ,  Ji-Young Kim

    IPC分类号： F21V9/04

    CPC分类号： G02B5/208 ,  G02B5/204 ,  H01J11/10 ,  H01J11/44 ,  H01J2211/444 ,  H01J2211/446 ,  H01J2211/448

    摘要： A filter 100 for a display device includes a transparent substrate 110; a near infrared ray blocking layer 120; and electromagnetic shielding layer 130; an external light blocking layer 140; and a color compensation layer 150. The near infrared ray blocking layer 120 is formed on the transparent substrate 110 and includes a metal thin film and a metal oxide thin film which are alternately layered, each of the metal thin film and the metal oxide thin film being layered one or more times. The electromagnetic shielding layer 130 is formed on the near infrared ray blocking layer 120 and includes a metal mesh pattern. The external light blocking layer 140 includes an external light blocking pattern 144, the external light blocking pattern including a plurality of external light blocking parts with a wedge shape which are filled with a light absorbing material and a conductive material. The color compensation layer 150 is formed on the external light blocking layer 140 and includes a polymer resin and at least two kinds of colorants selectively absorbing lights. The filter 100 has a transmittance of 5% or less at an 850 nm wavelength. The filter 100 has excellent performance in blocking near infrared rays and electromagnetic waves and high transmittance to visible light.

    摘要翻译： 用于显示装置的滤光器100包括透明基板110; 近红外线阻挡层120; 和电磁屏蔽层130; 外部遮光层140; 和颜色补偿层150.近红外线阻挡层120形成在透明基板110上，并且包括交替层叠的金属薄膜和金属氧化物薄膜，金属薄膜和金属氧化物薄膜 分层一次或多次。 电磁屏蔽层130形成在近红外线阻挡层120上并且包括金属网状图案。 外部遮光层140包括外部遮光图案144，外部遮光图案包括填充有光吸收材料和导电材料的多个具有楔形形状的外部遮光部分。 颜色补偿层150形成在外部遮光层140上，并且包括聚合物树脂和选择性吸收光的至少两种着色剂。 滤光器100在850nm波长下的透射率为5％以下。 过滤器100在阻挡近红外线和电磁波以及对可见光的高透射率方面具有优异的性能。

    Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same
    105.
    发明授权
    Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same 有权
    在由其制造的集成电路器件中制造集成电路器件中的凹槽晶体管和凹槽晶体管的方法

    公开(公告)号：US07365390B2

    公开(公告)日：2008-04-29

    申请号：US11691044

    申请日：2007-03-26

    申请人： Ji-Young Kim

    发明人： Ji-Young Kim

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

    CPC分类号： H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823487

    摘要： Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation region and the sidewall of the gate trench, is etched to expose the remaining substrate region. Thereafter, the exposed portion of the remaining substrate region is removed to form a substantially flat bottom of the gate trench. The recess transistor manufactured by the provided method has the same channel length regardless of the locations of the recess transistor in an active region.

    摘要翻译： 提供了一种在集成电路器件中制造凹槽晶体管的方法。 在所提供的方法中，蚀刻与栅极沟槽的侧壁接触的器件隔离区域和残留在器件隔离区域的侧壁与栅极沟槽的侧壁之间的衬底区域，以露出剩余的衬底区域。 此后，去除剩余的衬底区域的暴露部分以形成栅极沟槽的基本平坦的底部。 通过所提供的方法制造的凹槽晶体管具有相同的沟道长度，而与有源区中的凹槽晶体管的位置无关。

    Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same
    107.
    发明授权
    Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same 有权
    垂直双通道绝缘体上硅晶体管及其制造方法

    公开(公告)号：US07262462B2

    公开(公告)日：2007-08-28

    申请号：US11246106

    申请日：2005-10-11

    申请人： Ji-Young Kim ,  Jin-Jun Park

    发明人： Ji-Young Kim ,  Jin-Jun Park

    IPC分类号： H01L29/76

    CPC分类号： H01L29/78696 ,  H01L29/66787

    摘要： A vertical double channel silicon-on-insulator (SOI) field-effect-transistor (FET) includes a pair of two vertical semiconductor layers in contact with a pair of parallel shallow trench isolation layers on a substrate, a source, a drain and a channel region on each of the pair of vertical semiconductor layers with corresponding regions on the pair of vertical semiconductor layers facing each other in alignment, a gate oxide on the channel region of both of the pair of the vertical semiconductor layers, and a gate electrode, a source electrode, and a drain electrode electrically connecting the respective regions of the pair of vertical semiconductor layers.

    摘要翻译： 垂直双通道绝缘体上硅（SOI）场效应晶体管（FET）包括与衬底上的一对平行浅沟槽隔离层接触的一对两个垂直半导体层，源极，漏极和漏极 所述一对垂直半导体层中的每一个上的沟道区域与所述一对垂直半导体层中的对置区域对准，所述一对垂直半导体层中的两个沟道区上的栅极氧化物和栅电极， 源极电极和漏电极，电连接所述一对垂直半导体层的各个区域。

    Method of forming dual gate dielectric layer
    108.
    发明申请
    Method of forming dual gate dielectric layer 有权
    形成双栅介电层的方法

    公开(公告)号：US20070102767A1

    公开(公告)日：2007-05-10

    申请号：US11616836

    申请日：2006-12-27

    申请人： Min-Hee CHO ,  Ji-Young Kim

    发明人： Min-Hee CHO ,  Ji-Young Kim

    IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

    CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823462

    摘要： A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer is formed on a first region. The semiconductor device also includes a second dielectric layer having a dielectric constant higher than that of the first dielectric layer. The second dielectric layer is formed on both the first region and a second region.

    摘要翻译： 半导体器件包括提高半导体器件的性能的双栅介质层。 半导体器件包括在半导体衬底上具有预定厚度的第一电介质层。 第一介电层形成在第一区域上。 半导体器件还包括具有高于第一介电层的介电常数的介电常数的第二电介质层。 第二介电层形成在第一区域和第二区域两者上。

    Recess gate transistor structure for use in semiconductor device and method thereof
    109.
    发明授权
    Recess gate transistor structure for use in semiconductor device and method thereof 有权
    用于半导体器件的栅极晶体管结构及其方法

    公开(公告)号：US07164170B2

    公开(公告)日：2007-01-16

    申请号：US10968599

    申请日：2004-10-18

    申请人： Ji-Young Kim

    发明人： Ji-Young Kim

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66621 ,  H01L29/7834

    摘要： An inner spacer is formed in a sidewall of a gate in contact with a first active region that is electrically connected to an upper capacitor, thereby reducing a gate induced drain leakage (GIDL). A structure of a recess gate transistor includes a gate insulation layer, a gate electrode, a first gate spacer, a second gate spacer and source/drain regions. The gate insulation layer is formed within a recess. The gate electrode is surrounded by the gate insulation layer and is extended from within the recess. The first gate spacer is spaced with a predetermined distance horizontally with a portion of the gate insulation layer, being formed in a sidewall of the gate electrode. The second gate spacer is formed in another part of the sidewall of the gate electrode. The source/drain regions are formed mutually oppositely on first and second active regions with the gate electrode therebetween.

    摘要翻译： 内部间隔件形成在栅极的侧壁中，与与上部电容器电连接的第一有源区域接触，由此减小栅极引起漏极泄漏（GIDL）。 凹槽栅极晶体管的结构包括栅极绝缘层，栅极电极，第一栅极间隔物，第二栅极间隔物和源极/漏极区域。 栅极绝缘层形成在凹部内。 栅电极被栅绝缘层包围，并从凹槽内延伸。 第一栅极间隔物与门极绝缘层的一部分水平地间隔预定距离，形成在栅电极的侧壁中。 第二栅极间隔物形成在栅电极的侧壁的另一部分中。 源极/漏极区域在第一和第二有源区域上彼此相对地形成，栅电极在它们之间。

    Method of forming dual gate dielectric layer
    110.
    发明申请
    Method of forming dual gate dielectric layer 有权
    形成双栅介电层的方法

    公开(公告)号：US20050282352A1

    公开(公告)日：2005-12-22

    申请号：US10964170

    申请日：2004-10-12

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234

    CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823462

    摘要： A method of forming a dual gate dielectric layer increases a performance of a semiconductor device by using a dielectric layer having a high dielectric constant, including forming a first dielectric layer having a predetermined thickness on a semiconductor substrate; removing the first dielectric layer formed on a second region, but leaving this layer on a first region; and forming a second dielectric layer having a dielectric constant higher than that of the first dielectric layer, on the first and second regions.

    摘要翻译： 通过使用具有高介电常数的介电层，包括在半导体衬底上形成具有预定厚度的第一介质层，形成双栅介质层的方法提高了半导体器件的性能; 去除形成在第二区域上的第一介电层，但将该层留在第一区域上; 以及在所述第一和第二区域上形成具有高于所述第一介电层的介电常数的介电常数的第二电介质层。