公开(公告)号：US20090085074A1

公开(公告)日：2009-04-02

申请号：US11866350

申请日：2007-10-02

申请人： Shih Tzung Su ,  Jun Zeng ,  Poi Sun ,  Kao Way Tu ,  Tai Chiang Chen ,  Long Lv ,  Xin Wang

发明人： Shih Tzung Su ,  Jun Zeng ,  Poi Sun ,  Kao Way Tu ,  Tai Chiang Chen ,  Long Lv ,  Xin Wang

IPC分类号： H01L29/00 ,  H01L21/425

CPC分类号： H01L29/7811 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： In accordance with the invention, a trench MOSFET semiconductor device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first mask to define openings for the trench gate and termination; utilizing a second mask as a source mask with openings determining the size and shape of a diffused source junction depth; utilizing a third mask as a contact mask to define contact hole openings; and utilizing a fourth mask as a metal mask, whereby only the first, second, third and fourth masks are utilized in the manufacture of the trench MOSFET semiconductor device.

摘要翻译： 根据本发明，根据包括以下步骤的方法制造沟槽MOSFET半导体器件：提供重掺杂的N +硅衬底; 利用第一掩模来限定沟槽栅极和终端的开口; 利用第二掩模作为源掩模，其具有确定扩散源结深度的尺寸和形状的开口; 利用第三掩模作为接触掩模来限定接触孔开口; 并且利用第四掩模作为金属掩模，由此在制造沟槽MOSFET半导体器件中仅利用第一，第二，第三和第四掩模。

公开(公告)号：US20080251383A1

公开(公告)日：2008-10-16

申请号：US12064630

申请日：2006-08-23

申请人： Daniel Sobek ,  Jun Zeng

发明人： Daniel Sobek ,  Jun Zeng

IPC分类号： G01N27/00

CPC分类号： B01L3/502792 ,  B01L3/50273 ,  B01L3/502738 ,  B01L2300/0645 ,  B01L2300/069 ,  B01L2300/089 ,  B01L2400/0415 ,  B01L2400/0448 ,  B01L2400/06 ,  F04B19/006 ,  G01N33/4905

摘要： A microfluidic liquid stream configuration system is provided including providing a substrate; forming a first co-planar electrode and a second co-planar electrode on the substrate; applying a dielectric layer, with a controlled surface energy, on the first co-planar electrode and the second co-planar electrode; forming an input reservoir on the first co-planar electrode and a second co-planar electrode; supplying a liquid in the input reservoir for analysis; and imposing an electric field, an electric field gradient, or a combination thereof on the liquid for respectively driving surface charge or dipole moments in the liquid for configuring a liquid stream.

摘要翻译： 提供了一种微流体液流配置系统，包括提供基板; 在所述基板上形成第一共面电极和第二共面电极; 在所述第一共平面电极和所述第二共面电极上施加具有受控表面能的电介质层; 在所述第一共平面电极和第二共面电极上形成输入容器; 在输入容器中供应液体进行分析; 并在液体上施加电场，电场梯度或其组合，以分别驱动用于构成液体流的液体中的表面电荷或偶极矩。

公开(公告)号：US20060216895A1

公开(公告)日：2006-09-28

申请号：US11165077

申请日：2005-06-23

申请人： Jun Zeng ,  Po-I Sun

发明人： Jun Zeng ,  Po-I Sun

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/76838 ,  H01L29/66348 ,  H01L29/66621 ,  H01L29/7834

摘要： A power semiconductor device includes a substrate, a gate oxide layer, a gate bus layer, an inter-layer dielectric layer and a metal bus layer. The substrate has a trench structure therein. The gate oxide layer is formed on surfaces of the substrate and the trench structure. The gate bus layer is formed on the gate oxide layer inside the trench structure. The inter-layer dielectric layer is formed on the gate oxide layer and a portion of the gate bus layer, thereby defining a contact window. The metal bus layer is formed on the inter-layer dielectric layer and the trench structure, and connected to the gate bus layer via the contact window.

摘要翻译： 功率半导体器件包括衬底，栅极氧化物层，栅极总线层，层间电介质层和金属母线层。 衬底在其中具有沟槽结构。 栅极氧化层形成在衬底和沟槽结构的表面上。 栅极总线层形成在沟槽结构内部的栅极氧化物层上。 层间电介质层形成在栅极氧化物层和栅极总线层的一部分上，由此限定接触窗口。 金属总线层形成在层间电介质层和沟槽结构上，并通过接触窗口连接到栅极总线层。

公开(公告)号：US20050184318A1

公开(公告)日：2005-08-25

申请号：US11104164

申请日：2005-04-12

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/7813 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of the semiconductor layer laterally adjacent the dielectric layer are removed so that an upper portion thereof extends outwardly from the semiconductor layer. Spacers are formed laterally adjacent the outwardly extending upper portion of the dielectric layer, the spacers are used as a self-aligned mask for defining source/body contact regions.

摘要翻译： 制造功率MOSFET的方法包括在半导体层中形成沟槽，形成衬底沟槽的栅极电介质层，在沟槽的下部形成栅极导电层，形成电介质层以填充该沟槽的上部 沟。 去除与电介质层横向相邻的半导体层的部分，使得其上部从半导体层向外延伸。 间隔件横向邻近介质层的向外延伸的上部形成，间隔件用作用于限定源/体接触区域的自对准掩模。

公开(公告)号：US06929988B2

公开(公告)日：2005-08-16

申请号：US10678444

申请日：2003-10-01

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78 ,  H01L29/80

CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/749

摘要： The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

摘要翻译： 功率器件的蜂窝结构包括具有高掺杂漏极区的衬底。 在衬底上有相同掺杂的更轻掺杂的外延层。 外延层上方是由相反型掺杂形成的阱区。 覆盖阱是重掺杂的第一导电类型的上源层。 沟槽结构包括侧壁氧化物或覆盖沟槽侧壁的其它合适的绝缘材料。 沟槽的底部填充有掺杂多晶硅屏蔽层。 诸如氮化硅的层间电介质覆盖屏蔽。 栅极区域由另一层掺杂多晶硅形成。 第二层间电介质（通常为硼磷硅玻璃（BPSG））覆盖栅极。 在工作中，当适当的电压施加到栅极时，电流通过阱中的沟道在源极和漏极之间垂直流动。

公开(公告)号：US06921957B2

公开(公告)日：2005-07-26

申请号：US10335022

申请日：2002-12-31

申请人： Jun Zeng ,  Ming-Jiang Zhou ,  Tzong-Shiann Wu

发明人： Jun Zeng ,  Ming-Jiang Zhou ,  Tzong-Shiann Wu

IPC分类号： H01L21/329 ,  H01L27/06 ,  H01L29/78 ,  H01L29/872 ,  H01L29/72

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/66143 ,  H01L29/7806 ,  H01L29/872

摘要： A new low forward voltage drop Schottky barrier diode and its manufacturing method are provided. The method includes steps of providing a substrate, forming plural trenches on the substrate, and forming a metal layer on the substrate having plural trenches thereon to form a barrier metal layer between the substrate and the surface metal layer for forming the Schottky barrier diode.

摘要翻译： 提供了一种新的低正向压降肖特基势垒二极管及其制造方法。 该方法包括以下步骤：提供衬底，在衬底上形成多个沟槽，并在其上具有多个沟槽的衬底上形成金属层，以在衬底和用于形成肖特基势垒二极管的表面金属层之间形成阻挡金属层。

公开(公告)号：US06916712B2

公开(公告)日：2005-07-12

申请号：US10039319

申请日：2001-11-09

申请人： Christopher B. Kocon ,  Jun Zeng

发明人： Christopher B. Kocon ,  Jun Zeng

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397

摘要： An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.

摘要翻译： 改进的沟槽MOS门控器件包括单晶半导体衬底，其上配置有掺杂的上层。 上层在上表面包括具有第一极性的多个重掺杂体区域，并且覆盖在漏极区域上。 上层还在其上表面包括多个重掺杂的源极区域，其具有与主体区域A相反的第二极性。栅极沟槽从上层的上表面延伸到漏极区域，并将一个源极区域与另一个源区域分离。 沟槽具有包括介电材料层的底板和侧壁，并且包含填充到选定电平的导电栅极材料和覆盖栅极材料并基本上填充沟槽的介电材料隔离层。 因此，沟槽中的上层电介质材料的上表面与上层的上表面基本上共面。 用于形成改进的MOS栅极器件的工艺提供了一种器件，其栅极沟槽被填充到具有导电栅极材料的选定的电平，在其上形成隔离电介质层，其上表面与上层的上表面基本共面 的设备。

公开(公告)号：US06784505B2

公开(公告)日：2004-08-31

申请号：US10138913

申请日：2002-05-03

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L2994

CPC分类号： H01L29/7811 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.

摘要翻译： 通过沟槽底部的掺杂剂注入将低功率沟槽MOSFET器件中的漂移区域合并在一起可以使用非常小的单元间距，导致非常高的沟道密度和均匀掺杂的沟道，从而显着降低 渠道阻力。 通过适当选择植入剂量和漂移区域的退火参数，可以严密控制器件的沟道长度，并且可以使沟道掺杂高度均匀。 与常规器件相比，阈值电压降低，沟道电阻降低，并且漂移区导通电阻也降低。 实现合并的漂移区域需要结合新的边缘终端设计，使得由P外延层和N +基底形成的PN结可以在晶片的边缘端接。

公开(公告)号：US06677202B2

公开(公告)日：2004-01-13

申请号：US09765177

申请日：2001-01-18

申请人： Dexter Elson Semple ,  Jun Zeng

发明人： Dexter Elson Semple ,  Jun Zeng

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/0657 ,  H01L29/4232 ,  H01L29/4238

摘要： A power MOS device that has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions. In a process for forming a power MOS device with increased channel width on a semiconductor substrate having a doped upper layer of a first conduction type, a stripe mask is formed on an upper surface of the upper layer, and the upper surface is selectively etched to form a corrugated surface comprising a plurality of parallel corrugations. Following removal of the stripe mask, an insulating layer is formed on the corrugated surface, and an overlying conductive layer is formed on the insulating layer, the insulating and conductive layers comprising a corrugated gate region disposed transversely to the parallel corrugations of the upper surface. A dopant of a second, opposite conduction type is implanted to form a doped well region in the upper layer, and a dopant of the first conduction type is implanted into a portion of the corrugated surface adjacent to the gate, thereby forming a heavily doped source region in the upper layer. In an alternative procedure for forming a gate, a gate trench having a floor comprising parallel corrugations that substantially correspond to the corrugations in the upper surface is etched into the upper layer. Following lining of the trench floor and sidewalls with an insulating layer, the trench is substantially filled with a conductive material to form a gate trench. A dopant of the first conduction type is implanted into a portion of the corrugated surface adjacent to the gate region, thereby forming a heavily doped source region in the upper layer.

公开(公告)号：US06638826B2

公开(公告)日：2003-10-28

申请号：US10195984

申请日：2002-07-16

申请人： Jun Zeng ,  Gary M. Dolny ,  Christopher B. Kocon ,  Linda S. Brush

发明人： Jun Zeng ,  Gary M. Dolny ,  Christopher B. Kocon ,  Linda S. Brush

IPC分类号： H01L21336

CPC分类号： H01L29/7802 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/7813

摘要： An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches. A groove in each of the highly doped source regions extends through the source regions into the well region and terminates in a nadir. A highly doped body region of a first conductance type is disposed in the well region adjacent both to the nadir of one or more of the grooves and to adjacent source regions penetrated by the grooves. A conductive layer is disposed over the substrate and electrically contacts the body and source regions. A process for fabricating a device produces an MOS power device that avoids the loss of channel width and provides reduced channel resistance without sacrificing device ruggedness and dynamic characteristics.

摘要翻译： MOS功率器件的衬底包括具有上表面和下面的漏极区的上层，设置在漏极区上的上层中的第一导电类型的阱区，以及多个间隔开的掩埋栅， 包括从上层的上表面穿过阱区延伸到漏区的沟槽。 每个沟槽包括衬在其表面上的绝缘材料，将其下部填充到基本上在上层的上表面下方的选定水平的导电材料，以及基本上填充沟槽其余部分的绝缘材料。 第二导电类型的多个高掺杂源区被设置在邻近每个沟槽的上部的上层中，每个源区从上表面延伸到上层中的深度，以提供源区和 沟槽中的导电材料。 每个高掺杂源区域中的沟槽延伸穿过源区域进入阱区域并终止于最低点。 第一导电类型的高掺杂体区域设置在与一个或多个凹槽的最低点相邻的阱区域中以及与沟槽穿透的相邻源极区域相邻的阱区域中。 导电层设置在衬底上并与主体区域和源区域电接触。 制造器件的工艺产生了MOS功率器件，其避免了沟道宽度的损失，并且在不牺牲器件耐用性和动态特性的情况下提供降低的沟道电阻。