公开(公告)号：US10825528B2

公开(公告)日：2020-11-03

申请号：US15985973

申请日：2018-05-22

Applicant: Micron Technology, Inc.

Inventor： Akira Goda

IPC: G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/10 ,  G11C16/04

Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

公开(公告)号：US10825523B2

公开(公告)日：2020-11-03

申请号：US16667465

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

公开(公告)号：US10796778B2

公开(公告)日：2020-10-06

申请号：US16694043

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/06 ,  G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C8/08

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US10651282B2

公开(公告)日：2020-05-12

申请号：US16168470

申请日：2018-10-23

Applicant: Micron Technology, Inc.

Inventor： Minsoo Lee ,  Akira Goda

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/764 ,  H01L29/788 ,  H01L29/423 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

公开(公告)号：US20190354421A1

公开(公告)日：2019-11-21

申请号：US15982653

申请日：2018-05-17

Applicant: Micron Technology, Inc.

Inventor： Kevin R. Brandt ,  William C. Filipiak ,  Michael G. McNeeley ,  Kishore K. Muchherla ,  Sampath K. Ratnam ,  Akira Goda ,  Todd A. Marquart

IPC: G06F11/07 ,  G11C29/10

Abstract: Performing a first set of scans on a memory device in a memory system with a first time interval between each scan of the first set of scans to detect errors on the memory device, determining, from performing the first set of scans, that a rate of errors being detected on the memory device is changing, and performing a second set of scans with a second time interval between each scan of the second set of scans to detect errors on the memory device, in response to determining that the rate of errors being detected on the memory device is changing, wherein the second time interval is different than the first time interval.

公开(公告)号：US20190295668A1

公开(公告)日：2019-09-26

申请号：US16435996

申请日：2019-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Goda ,  Yijie Zhao ,  Krishna Parat

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

Abstract: Memory devices including a controller configured to cause the memory device to apply a positive first voltage level to a first data line selectively connected to a first string of series-connected memory cells while applying a second voltage level, higher than the first voltage level, to a second data line selectively connected to a second string of series-connected memory cells; while applying the first voltage level to the first data line and applying the second voltage level to the second data line, applying a third voltage level to a particular access line coupled to a memory cell of a first string of series-connected memory cells selected for programming, wherein a differential between the third voltage level and the first voltage level is configured to increase a threshold voltage of the memory cell selected for programming, as well as other apparatus containing similar memory devices.

公开(公告)号：US20190288002A1

公开(公告)日：2019-09-19

申请号：US16419736

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11573 ,  G11C16/04 ,  H01L27/11529 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11524 ,  G11C16/34 ,  G11C16/14 ,  H01L21/02 ,  H01L27/1157

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

公开(公告)号：US20190279715A1

公开(公告)日：2019-09-12

申请号：US16237337

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  G11C16/06 ,  G11C16/34 ,  G11C16/14 ,  G11C16/12 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US10360979B2

公开(公告)日：2019-07-23

申请号：US16036549

申请日：2018-07-16

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/16 ,  G11C16/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105 ,  H01L27/115 ,  H01L49/02

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US20190157092A1

公开(公告)日：2019-05-23

申请号：US16168470

申请日：2018-10-23

Applicant: Micron Technology, Inc

Inventor： Minsoo Lee ,  Akira Goda

IPC: H01L21/28 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66 ,  H01L27/11556 ,  H01L29/788 ,  H01L21/764 ,  H01L27/11519

Abstract: Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.