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公开(公告)号：US20190065109A1
公开(公告)日：2019-02-28
申请号：US15693128
申请日：2017-08-31
Applicant: Micron Technology, Inc.
Inventor： Matthew A. Prather , Frank F. Ross
IPC: G06F3/06
Abstract: A memory system is provided. The memory system includes a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command. The second latency differs from the first latency by a latency difference. The memory system further includes a host operably coupled to the first and second memory devices. The host is configured to send the first command to the first memory device at a first time, and to send the second command to the second memory device at a second time. The first time and the second time are separated by a delay corresponding to the latency difference.
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公开(公告)号：US12300349B2
公开(公告)日：2025-05-13
申请号：US18087328
申请日：2022-12-22
Applicant: Micron Technology, Inc.
Inventor： Jasper S. Gibbons , Matthew A. Prather , Brent Keeth , Frank F Ross , Daniel Benjamin Stewart , Randall J. Rooney
Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.
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公开(公告)号：US11948655B2
公开(公告)日：2024-04-02
申请号：US17726139
申请日：2022-04-21
Applicant: Micron Technology, Inc.
CPC classification number: G11C29/4401 , G11C29/18 , G11C29/787 , H03K19/20 , G11C2029/4402
Abstract: Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.
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公开(公告)号：US11867726B2
公开(公告)日：2024-01-09
申请号：US16985156
申请日：2020-08-04
Applicant: Micron Technology, Inc.
Inventor： Daniel B. Stewart , Eric J. Stave , Matthew A. Prather
IPC: G01R13/32
CPC classification number: G01R13/32
Abstract: A method of operating an oscilloscope is disclosed. The method comprises providing a bit stream comprising pseudo-random data to an oscilloscope across a data path characterized by sufficient signal degradation to prevent the oscilloscope from reliably triggering a sweep of an eye pattern based on receiving the pseudo-random data; inserting a predetermined sequence of bits into the bit stream at predetermined periodic intervals to open the eye pattern sufficiently during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye pattern; and generating the eye pattern based at least in part on the pseudo-random data and excluding the predetermined sequence of bits from the sweep of the eye pattern. Oscilloscopes configured to trigger according to a predetermined system of bits at predetermined intervals are also disclosed.
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公开(公告)号：US20240004755A1
公开(公告)日：2024-01-04
申请号：US18195374
申请日：2023-05-10
Applicant: Micron Technology, Inc.
Inventor： Randall J. Rooney , Matthew A. Prather
IPC: G06F11/10 , G11C11/408 , G11C11/406
CPC classification number: G06F11/1068 , G11C11/4087 , G11C11/406
Abstract: Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.
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Patent Agency Ranking
公开(公告)号：US11854655B2
公开(公告)日：2023-12-26
申请号：US17534230
申请日：2021-11-23
Applicant: Micron Technology, Inc.
Inventor： Matthew A. Prather , Randall J. Rooney
IPC: G11C7/10 , G06F11/30 , G11C11/4093
CPC classification number: G11C7/1045 , G06F11/3037 , G06F11/3058 , G11C7/1051 , G11C7/1078 , G11C11/4093
Abstract: Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.
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公开(公告)号：US20230343409A1
公开(公告)日：2023-10-26
申请号：US17726139
申请日：2022-04-21
Applicant: Micron Technology, Inc.
CPC classification number: G11C29/4401 , G11C29/18 , G11C29/787 , H03K19/20 , G11C2029/4402
Abstract: Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.
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公开(公告)号：US11762582B2
公开(公告)日：2023-09-19
申请号：US17035259
申请日：2020-09-28
Applicant: Micron Technology, Inc.
Inventor： Frank F. Ross , Matthew A. Prather
CPC classification number: G06F3/0659 , G06F3/0613 , G06F3/0688 , G06F12/0253
Abstract: The present disclosure includes apparatuses and methods related to performing background operations in memory. A memory device can be configured to perform background operations while another memory device in a memory system and/or on a common memory module is busy performing commands received from a host coupled to the memory system and/or common memory module. An example apparatus can include a first memory device, wherein the first memory device can include an array of memory cells and a controller configured to perform a background operation on the first memory device in response to detecting a command from a host to a second memory device.
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公开(公告)号：US20230206969A1
公开(公告)日：2023-06-29
申请号：US18086991
申请日：2022-12-22
Applicant: Micron Technology, Inc.
Inventor： Sujeet V. Ayyapureddi , Brent Keeth , Matthew A. Prather
CPC classification number: G11C7/109 , G11C7/1084 , G11C7/222
Abstract: Methods, systems, and devices for buffer configurations for communications between memory dies and a host device are described. A memory device may include a buffer having a first interface coupled with a host device and a second interface coupled with a memory die of the memory device. The first interface may communicate information with the host device at a first frequency and according to a first signaling scheme, and the second interface may communicate information with the memory die at a second frequency and according to a second signaling scheme. The first frequency may be higher than the second frequency, and the second signaling scheme may include a greater quantity of voltage levels than the first signaling scheme.
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公开(公告)号：US20230127970A1
公开(公告)日：2023-04-27
申请号：US18087328
申请日：2022-12-22
Applicant: Micron Technology, Inc.
Inventor： Jasper S. Gibbons , Matthew A. Prather , Brent Keeth , Frank F. Ross , Daniel Benjamin Stewart , Randall J. Rooney
Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.
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