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    Information processing apparatus, information processing method, and program to calculate position and posture of an object having a three-dimensional shape
    101.
    发明授权
    Information processing apparatus, information processing method, and program to calculate position and posture of an object having a three-dimensional shape 有权
    用于计算具有三维形状的物体的位置和姿势的信息处理装置，信息处理方法和程序

    公开(公告)号：US09317735B2

    公开(公告)日：2016-04-19

    申请号：US13993496

    申请日：2011-12-09

    申请人： Daisuke Watanabe

    发明人： Daisuke Watanabe

    IPC分类号： G06K9/00 ,  G06T7/00

    CPC分类号： G06K9/00201 ,  G06T7/75 ,  G06T2207/10028

    摘要： An information processing apparatus includes a first setting unit setting a relative position-posture relationship between a 3D-shaped model of an object and a viewpoint from which the model is observed as a base position-posture, a detector detecting geometric features of the model observed from the viewpoint in the base position-posture as base geometric features, a second setting unit setting a relative position-posture relationship between the model and a viewpoint as a reference position-posture, a retrieval unit retrieving reference geometric features corresponding to the base geometric features of the model observed from the viewpoint in the reference position-posture, a first calculation unit calculating similarity degrees between the base geometric features and the reference geometric features, and a second calculation unit calculating evaluation values of correspondences between the base geometric features and the reference geometric features in accordance with the similarity degrees.

    摘要翻译： 信息处理设备包括：第一设置单元，设置物体的3D形模型与观察模型的视点之间的相对位置姿势关系作为基本位置姿势，检测器检测所观察模型的几何特征 从作为基础几何特征的基本位置姿势的观点来看，设定作为基准位置姿势的模型与视点之间的相对位置姿势关系的第二设定单元，检索与基本几何特征对应的基准几何特征的检索单元 从参考姿势姿势的观点观察的模型的特征，计算基本几何特征与参考几何特征之间的相似度的第一计算单元，以及计算基本几何特征与基准几何特征之间的对应关系的评估值的第二计算单元 参考几何特征按照相似度 度。

    Test apparatus with voltage margin test
    103.
    发明授权
    Test apparatus with voltage margin test 有权
    具有电压裕度测试的测试装置

    公开(公告)号：US08896332B2

    公开(公告)日：2014-11-25

    申请号：US13316373

    申请日：2011-12-09

    申请人： Masahiro Ishida ,  Daisuke Watanabe ,  Toshiyuki Okayasu ,  Kiyotaka Ichiyama

    发明人： Masahiro Ishida ,  Daisuke Watanabe ,  Toshiyuki Okayasu ,  Kiyotaka Ichiyama

    IPC分类号： G01R31/00 ,  G01R31/26

    CPC分类号： G01R31/31924

    摘要： A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR.

    摘要翻译： 模式发生器产生表示要提供给DUT的测试信号的模式信号。 驱动器产生具有对应于模式信号的电平的测试信号，并且将如此产生的测试信号输出到DUT。 电压调制器在预定电压范围内改变从驱动器DR输出的测试信号的电压电平。

    Semiconductor wafer, semiconductor circuit, substrate for testing and test system
    104.
    发明授权
    Semiconductor wafer, semiconductor circuit, substrate for testing and test system 失效
    半导体晶圆，半导体电路，测试和测试系统基板

    公开(公告)号：US08593166B2

    公开(公告)日：2013-11-26

    申请号：US12957168

    申请日：2010-11-30

    申请人： Daisuke Watanabe ,  Toshiyuki Okayasu

    发明人： Daisuke Watanabe ,  Toshiyuki Okayasu

    IPC分类号： G01R31/26

    CPC分类号： G01R31/31926 ,  G01R31/2889 ,  G01R31/318511 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A test system includes a test substrate that transmits/receives signals to/from a semiconductor wafer, and a control apparatus to control the test substrate. The semiconductor wafer includes an external terminal coupled to an external measurement circuit, a plurality of selecting wiring lines provided to receive/transmit signals to/from the corresponding the measuring points, and a selecting section that selects one of the selecting wiring lines and that allows signal transmission between the corresponding measuring point and the external terminal through the selected selecting wiring line. The test substrate includes a measurement circuit that is coupled to the external terminal of the semiconductor wafer and that measures an electrical characteristic of a signal transmitted through the selecting wiring line selected by the selecting section, and a control section that controls which one of the measurement wiring lines is to be selected by the selecting section in the semiconductor wafer.

    摘要翻译： 测试系统包括向/从半导体晶片发送/接收信号的测试基板，以及控制测试基板的控制装置。 半导体晶片包括耦合到外部测量电路的外部端子，设置成用于向/从相应的测量点接收/发送信号的多个选择布线，以及选择部分，其选择选择布线之一并且允许 通过所选择的选择布线在相应的测量点和外部端子之间进行信号传输。 测试基板包括耦合到半导体晶片的外部端子并测量通过选择部分选择的选择布线所传输的信号的电特性的测量电路，以及控制部分，其控制哪个测量 通过半导体晶片中的选择部分来选择布线。

    Timing generator
    106.
    发明授权
    Timing generator 失效
    定时发生器

    公开(公告)号：US08392145B2

    公开(公告)日：2013-03-05

    申请号：US13409030

    申请日：2012-02-29

    申请人： Daisuke Watanabe ,  Toshiyuki Okayasu

    发明人： Daisuke Watanabe ,  Toshiyuki Okayasu

    IPC分类号： G06F19/00

    CPC分类号： G01R31/31725 ,  G01R31/3016

    摘要： A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data.

    摘要翻译： 延迟设定数据发生器基于速率数据生成延迟设定数据。 参考预定义的单位延迟量，可变延迟电路将测试图形数据延迟由延迟设置数据确定的延迟时间。 第一速率数据以由单位延迟量确定的精度指定测试图案数据的周期。 第二速率数据指定具有比单位延迟量确定的精度高的测试图案数据的周期。 延迟设定数据发生器以由第二速率数据确定的比例以时分方式输出第一值和第二值，第一和第二值由第一速率数据确定。

    Memory device, manufacturing method for memory device and method for data writing
    107.
    发明授权
    Memory device, manufacturing method for memory device and method for data writing 失效
    存储器件，存储器件的制造方法和数据写入方法

    公开(公告)号：US08369126B2

    公开(公告)日：2013-02-05

    申请号：US12959298

    申请日：2010-12-02

    申请人： Toshiyuki Okayasu ,  Daisuke Watanabe

    发明人： Toshiyuki Okayasu ,  Daisuke Watanabe

    IPC分类号： G11C13/00

    CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521

    摘要： A memory device to which an electron beam is irradiated to store data therein is provided. The memory device includes a plurality of floating electrodes that store data through irradiation of the electron beam thereto, a charge amount detecting section that detects data stored in each of the floating electrodes based on a charge amount accumulated in each of the floating electrode.

    摘要翻译： 提供了一种存储器件，电子束照射到其上以存储数据。 存储装置包括通过照射电子束而存储数据的多个浮动电极，电荷量检测部，其基于在每个浮置电极中累积的电荷量来检测存储在每个浮置电极中的数据。

    Test apparatus and electronic device
    108.
    发明授权
    Test apparatus and electronic device 有权
    测试仪器和电子设备

    公开(公告)号：US08299810B2

    公开(公告)日：2012-10-30

    申请号：US12512933

    申请日：2009-07-30

    申请人： Daisuke Watanabe ,  Toshiyuki Okayasu

    发明人： Daisuke Watanabe ,  Toshiyuki Okayasu

    IPC分类号： G01R31/00

    CPC分类号： G01R31/31813 ,  G01R31/318385 ,  G01R31/318544

    摘要： Provided is a test apparatus that tests a device under test including an external interface circuit that transfers signals between an internal circuit inside a device and the outside of the device, the test apparatus comprising a pattern generating section that inputs, to the external interface circuit, a test pattern for testing the external interface circuit; an interface control section that causes the external interface circuit to loop back and output the test pattern; and an interface judging section that judges acceptability of the external interface circuit based on the test pattern looped back and output by the external interface circuit.

    摘要翻译： 提供一种测试装置，其测试包括在设备内部的内部电路和设备外部之间传送信号的外部接口电路的测试设备，所述测试设备包括：图案生成部分，其将外部接口电路， 用于测试外部接口电路的测试模式; 接口控制部，其使外部接口电路回路并输出测试图案; 以及接口判断部，其基于由外部接口电路回送并输出的测试模式来判断外部接口电路的可接受性。

    THREE-DIMENSIONAL MEASUREMENT APPARATUS, MODEL GENERATION APPARATUS, PROCESSING METHOD THEREOF, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM
    109.
    发明申请
    THREE-DIMENSIONAL MEASUREMENT APPARATUS, MODEL GENERATION APPARATUS, PROCESSING METHOD THEREOF, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM 有权
    三维测量装置，型号发生装置，其处理方法和非终端计算机可读存储介质

    公开(公告)号：US20120262455A1

    公开(公告)日：2012-10-18

    申请号：US13517293

    申请日：2011-02-23

    申请人： Daisuke Watanabe ,  Masakazu Fujiki ,  Shinji Uchiyama

    发明人： Daisuke Watanabe ,  Masakazu Fujiki ,  Shinji Uchiyama

    IPC分类号： G06T17/00

    CPC分类号： G06T7/75

    摘要： A three-dimensional measurement apparatus generates a plurality of view-point images obtained by observing a measurement object from a plurality of different view-points using a three-dimensional geometric model, detects edges of the measurement object from the plurality of view-point images as second edges, calculates respective reliabilities of first edges of the three-dimensional geometric model based on a result obtained when the second edges are associated with the first edges, weights each of the first edges based on the respective reliabilities, associates third edges detected from a captured image with the weighted first edges, and calculates a position and an orientation of the measurement object based on the association result.

    摘要翻译： 三维测量装置产生通过使用三维几何模型从多个不同观点观察测量对象而获得的多个视点图像，从多个视点图像检测测量对象的边缘 作为第二边缘，基于当第二边缘与第一边缘相关联时获得的结果来计算三维几何模型的第一边缘的相应可靠性，基于相应的可靠性来对每个第一边缘进行加权，将从第 具有加权的第一边缘的捕获图像，并且基于关联结果计算测量对象的位置和取向。

    TEST APPARATUS
    110.
    发明申请
    TEST APPARATUS 审中-公开
    测试仪器

    公开(公告)号：US20120146416A1

    公开(公告)日：2012-06-14

    申请号：US13311356

    申请日：2011-12-05

    申请人： Masahiro Ishida ,  Daisuke Watanabe ,  Masayuki Kawabata ,  Toshiyuki Okayasu

    发明人： Masahiro Ishida ,  Daisuke Watanabe ,  Masayuki Kawabata ,  Toshiyuki Okayasu

    IPC分类号： H02J1/10

    CPC分类号： G01R31/31924 ,  Y10T307/505

    摘要： A DUT comprises a notifying circuit configured to generate a notification signal which is used to notify an external circuit of an event that leads to a change in the operating current of the DUT before such an event occurs. A main power supply supplies electric power to a power supply terminal of the DUT. A power supply compensation circuit comprises a switch element which is controlled according to a control signal, and is configured to generate a compensation pulse current according to the on/off state of the switch element. A compensation control circuit receives the notification signal from the DUT, and outputs, to the power supply compensation circuit, a control signal which is used to control the switch element, and which is generated based upon at least the notification signal.

    摘要翻译： DUT包括通知电路，其被配置为产生通知信号，该通知信号用于在事件发生之前通知外部电路导致DUT的工作电流变化的事件。 主电源向DUT的电源端供电。 电源补偿电路包括根据控制信号控制的开关元件，并且被配置为根据开关元件的接通/断开状态产生补偿脉冲电流。 补偿控制电路接收来自DUT的通知信号，并且向电源补偿电路输出用于控制开关元件的控制信号，并且至少基于通知信号生成控制信号。