公开(公告)号：US20230197182A1

公开(公告)日：2023-06-22

申请号：US18108302

申请日：2023-02-10

Applicant: Micron Technology, Inc.

Inventor： Mark D. Ingram ,  Todd Jackson Plum ,  Scott E. Schaefer ,  Aaron P. Boehm ,  Scott D. Van De Graaff

IPC: G11C29/44 ,  G11C29/12 ,  G06F12/02

CPC classification number: G11C29/4401 ,  G11C29/12005 ,  G11C29/12015 ,  G06F12/0238 ,  G06F2212/7211 ,  G11C2207/2254 ,  G06F2212/7201

Abstract: Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

公开(公告)号：US11675662B2

公开(公告)日：2023-06-13

申请号：US17348211

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Jongtae Kwak ,  Aaron P. Boehm

IPC: G06F11/10 ,  G11C7/10

CPC classification number: G06F11/1072 ,  G06F11/1012 ,  G06F11/1052 ,  G11C7/1018

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

公开(公告)号：US20230063494A1

公开(公告)日：2023-03-02

申请号：US17883237

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G11C29/50

Abstract: Methods, systems, and devices for memory operations are described. A command may be received by a memory device and from a device. Both the device and the memory device may maintain counters of valid operations. A request for a value associated with a counter at the memory device may be received from the device. Based on receiving the request, a value of the counter may be transmitted to the device. The values of the counters may be compared to determine whether invalid data has been obtained by the device. Also, a pin associated with communicating error correction information may be coupled with a voltage source based on receiving a signal. The pin may remain coupled with the voltage source until a command is processed or an end of the signal. Whether the pin is coupled with the voltage source may indicate a validity of associated data.

公开(公告)号：US20230062939A1

公开(公告)日：2023-03-02

申请号：US17816320

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: H03M13/15 ,  G06F11/07 ,  H03M13/00

Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

公开(公告)号：US11586383B2

公开(公告)日：2023-02-21

申请号：US16579153

申请日：2019-09-23

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F3/06 ,  G06F21/79 ,  G06F12/14

Abstract: Methods, systems, and devices for command block management are described. A memory device may receive a command (e.g., from a host device). The memory device may determine whether the command is defined by determining if the command is included within a set of defined commands. In the case that a received command is absent from the set of defined commands (e.g., the command is undefined), the memory device may block the command from being decoded for execution by the memory device. In some cases, the memory device may switch from a first operation mode to a second operation mode based on receiving an undefined command. The second operation mode may restrict an operation of the memory device, while the first mode may be less restrictive, in some cases. Additionally or alternatively, the memory device may indicate the undefined command to another device (e.g., the host device).

公开(公告)号：US20230014955A1

公开(公告)日：2023-01-19

申请号：US17946183

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F3/06 ,  G11C11/4072 ,  G11C7/20

Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.

公开(公告)号：US20220358010A1

公开(公告)日：2022-11-10

申请号：US17869775

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F11/10 ,  G06F11/30 ,  G06F11/07

Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.

公开(公告)号：US11474698B2

公开(公告)日：2022-10-18

申请号：US17097766

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G11C11/4072 ,  G11C7/20 ,  G06F3/06

Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.

公开(公告)号：US20220139487A1

公开(公告)日：2022-05-05

申请号：US17502982

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/14 ,  G11C8/18

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.

公开(公告)号：US20220100428A1

公开(公告)日：2022-03-31

申请号：US17464334

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Todd Jackson Plum ,  Scott D. Van De Graaff ,  Scott E. Schaefer ,  Mark D. Ingram

IPC: G06F3/06

Abstract: Methods, systems, and devices for operating frequency monitoring for memory devices are described for monitoring one or more operating frequency ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more operating frequency ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.