公开(公告)号：US11145628B1

公开(公告)日：2021-10-12

申请号：US16825397

申请日：2020-03-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Adarsh Rajashekhar ,  Senaka Kanakamedala ,  Fei Zhou

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

公开(公告)号：US20210305266A1

公开(公告)日：2021-09-30

申请号：US16833378

申请日：2020-03-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yao-Sheng Lee ,  Senaka KANAKAMEDALA ,  Raghuveer S. Makala ,  Johann ALSMEIER

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  H01L21/768

Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, an etch stop material layer located over the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the etch stop material layer, inter-tier memory openings vertically extending through the second-tier alternating stack, the etch stop material layer, and the first-tier alternating stack, and memory opening fill structures each including a memory film and a vertical semiconductor channel located in the inter-tier memory openings. The material of the etch stop material layer is different from materials of the first insulating layers, the second insulating layers, the first electrically conductive layers, and the second electrically conductive layers.

公开(公告)号：US10985172B2

公开(公告)日：2021-04-20

申请号：US16251854

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun Ge ,  Yanli Zhang ,  Fei Zhou ,  Raghuveer S. Makala

IPC: H01L27/115 ,  H01L27/11568 ,  H01L27/1159 ,  H01L29/423 ,  H01L29/792 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

公开(公告)号：US20210036019A1

公开(公告)日：2021-02-04

申请号：US16910638

申请日：2020-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou ,  Seung-Yeul Yang

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel, a vertical stack of majority germanium layers each containing at least 51 atomic percent germanium, and a vertical stack of ferroelectric dielectric layers.

公开(公告)号：US10818542B2

公开(公告)日：2020-10-27

申请号：US16362895

申请日：2019-03-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Fei Zhou ,  Raghuveer S. Makala

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/11565 ,  H01L27/11519

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.

公开(公告)号：US10811431B1

公开(公告)日：2020-10-20

申请号：US16457721

申请日：2019-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Yanli Zhang

IPC: H01L27/11597 ,  H01L27/11587 ,  G11C11/22 ,  G11C5/06

Abstract: A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.

公开(公告)号：US20200279862A1

公开(公告)日：2020-09-03

申请号：US16290277

申请日：2019-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou ,  Rahul Sharangpani

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.

公开(公告)号：US10748925B1

公开(公告)日：2020-08-18

申请号：US16268183

申请日：2019-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Manabu Kakazu ,  Raghuveer S. Makala ,  Senaka Kanakamedala

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.

公开(公告)号：US10700086B2

公开(公告)日：2020-06-30

申请号：US16021899

申请日：2018-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Fei Zhou ,  Senaka Krishna Kanakamedala ,  Yao-Sheng Lee

IPC: H01L27/11582 ,  H01L21/02 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11565

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.

公开(公告)号：US10651196B1

公开(公告)日：2020-05-12

申请号：US16183920

申请日：2018-11-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Fei Zhou ,  Raghuveer S. Makala ,  Adarsh Rajashekhar

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

Abstract: A vertical repetition of a unit layer stack including an insulating layer, a sacrificial material layer, and a nucleation promoter layer is formed over a substrate. Memory stack structures are formed through the vertical repetition. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the nucleation promoter layers within the vertical repetition. Electrically conductive layers are formed in the backside recesses by selectively growing a metallic material from physically exposed surfaces of the nucleation promoter layers while suppressing growth of the metallic material from physically exposed surfaces of the insulating layers.