公开(公告)号：US11449741B2

公开(公告)日：2022-09-20

申请号：US16569647

申请日：2019-09-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Nha Nguyen ,  Vipin Tiwari ,  Nhan Do

IPC: G06N3/063 ,  G06N3/04 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/08

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.

公开(公告)号：US11409352B2

公开(公告)日：2022-08-09

申请号：US16354040

申请日：2019-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G11C16/04 ,  G06N3/08 ,  G06F17/16 ,  G11C11/54 ,  G06N3/04

Abstract: Numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.

公开(公告)号：US11158374B2

公开(公告)日：2021-10-26

申请号：US16930777

申请日：2020-07-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Nhan Do ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C16/04 ,  G06F17/16 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array. The analog memory array optionally is a vector-by-matrix multiplier in an analog neuromorphic memory system used in a deep learning neural network. One embodiment comprises measuring an operating temperature within a memory array and applying, by a temperature compensation block, a bias voltage to a terminal of a memory cell in the array, wherein the bias voltage is a function of the operating temperature.

公开(公告)号：US20210280239A1

公开(公告)日：2021-09-09

申请号：US16986812

申请日：2020-08-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan VU ,  Stephen TRINH ,  Stanley HONG ,  Anh LY ,  Vipin Tiwari

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/26 ,  G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

公开(公告)号：US20210174185A1

公开(公告)日：2021-06-10

申请号：US17181656

申请日：2021-02-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06N3/063 ,  G06N3/08 ,  G06F3/06 ,  G06F17/16

Abstract: Numerous output circuits are disclosed for an analog neural memory system for a deep learning neural network. In one embodiment, an adaptable neuron circuit receives output current from a neuron and converts it into a voltage. In another embodiment, a current sample and hold circuit samples an input current and generates an output current. In another embodiment, a voltage sample and hold circuit samples an input voltage and generates an output voltage.

公开(公告)号：US10755783B2

公开(公告)日：2020-08-25

申请号：US16183250

申请日：2018-11-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Nhan Do ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C16/04 ,  G06F17/16 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: Numerous embodiments are disclosed for providing temperature compensation and leakage compensation for an analog neuromorphic memory system used in a deep learning neural network. The embodiments for providing temperature compensation implement discreet or continuous adaptive slope compensation and renormalization for devices, reference memory cells, or selected memory cells in the memory system. The embodiments for providing leakage compensation within a memory cell in the memory system implement adaptive erase gate coupling or the application of a negative bias on a control gate terminal, a negative bias on a word line terminal, or a bias on a source line terminal.

公开(公告)号：US10699779B2

公开(公告)日：2020-06-30

申请号：US16382013

申请日：2019-04-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C16/04 ,  G11C11/54 ,  G06N3/04 ,  H01L29/423 ,  G11C16/14 ,  H01L27/11521 ,  G11C16/10

Abstract: A neural network device having a first plurality of synapses that includes a plurality of memory cells. Each memory cell includes a floating gate over a first portion of a channel region and a first gate over a second portion of the channel region. The memory cells are arranged in rows and columns. A plurality of first lines each electrically connect together the first gates in one of the memory cell rows, a plurality of second lines each electrically connect together the source regions in one of the memory cell rows, and a plurality of third lines each electrically connect together the drain regions in one of the memory cell columns. The first plurality of synapses receives a first plurality of inputs as electrical voltages on the plurality of third lines, and provides a first plurality of outputs as electrical currents on the plurality of second lines.

公开(公告)号：US10650893B2

公开(公告)日：2020-05-12

申请号：US16550248

申请日：2019-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11521 ,  H01L29/788 ,  G06N3/08

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US10607710B2

公开(公告)日：2020-03-31

申请号：US16414714

申请日：2019-05-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/04 ,  G06N3/08 ,  G11C16/30 ,  G11C16/26 ,  G11C11/54

Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.

公开(公告)号：US20200066345A1

公开(公告)日：2020-02-27

申请号：US16183250

申请日：2018-11-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Nhan Do ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C16/04 ,  G06F17/16 ,  G06N3/063

Abstract: Numerous embodiments are disclosed for providing temperature compensation and leakage compensation for an analog neuromorphic memory system used in a deep learning neural network. The embodiments for providing temperature compensation implement discreet or continuous adaptive slope compensation and renormalization for devices, reference memory cells, or selected memory cells in the memory system. The embodiments for providing leakage compensation within a memory cell in the memory system implement adaptive erase gate coupling or the application of a negative bias on a control gate terminal, a negative bias on a word line terminal, or a bias on a source line terminal.