公开(公告)号：US20210280239A1

公开(公告)日：2021-09-09

申请号：US16986812

申请日：2020-08-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan VU ,  Stephen TRINH ,  Stanley HONG ,  Anh LY ,  Vipin Tiwari

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/26 ,  G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

公开(公告)号：US20220319620A1

公开(公告)日：2022-10-06

申请号：US17841411

申请日：2022-06-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Thuan VU ,  Stephen TRINH ,  Stanley HONG ,  Anh LY ,  Steven LEMKE ,  Nha NGUYEN ,  Vipin TIWARI ,  Nhan DO

IPC: G11C16/34 ,  G11C16/10 ,  G06N3/063 ,  G06F3/06 ,  G06N3/08 ,  G11C16/26 ,  G11C29/10

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method is disclosed of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.

公开(公告)号：US20210280240A1

公开(公告)日：2021-09-09

申请号：US16987101

申请日：2020-08-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  VIPIN Tiwari

IPC: G11C11/54 ,  G11C16/28 ,  G11C16/04 ,  H03F3/00 ,  H03M1/16 ,  H03M1/38 ,  G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.

公开(公告)号：US20240112729A1

公开(公告)日：2024-04-04

申请号：US18076129

申请日：2022-12-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Stephen TRINH ,  Stanley HONG ,  Thuan VU ,  Anh LY ,  Fan LUO

IPC: G11C11/56 ,  G06N3/04 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G06N3/04 ,  G11C11/5671 ,  G11C16/10 ,  G11C2216/04

Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.

公开(公告)号：US20240105263A1

公开(公告)日：2024-03-28

申请号：US18536123

申请日：2023-12-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Thuan VU ,  Stanley HONG ,  Stephen TRINH ,  Anh LY ,  Nhan DO ,  Mark REITEN

IPC: G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

Abstract: In one example, a non-volatile memory system comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.

公开(公告)号：US20140282348A1

公开(公告)日：2014-09-18

申请号：US13830267

申请日：2013-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hung Quoc NGUYEN ,  Hieu Van TRAN ,  Hung Thanh NGUYEN ,  Anh LY ,  Thuan VU

IPC: G06F17/50

CPC classification number: G11C16/08 ,  G06F17/5081 ,  G11C7/062 ,  G11C8/10 ,  G11C11/1673 ,  G11C13/004 ,  G11C16/26 ,  G11C16/28

Abstract: Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.

Abstract translation: 公开了用于高级纳米闪存器件中的感测电路的改进的PMOS和NMOS晶体管设计。

公开(公告)号：US20250104783A1

公开(公告)日：2025-03-27

申请号：US18974776

申请日：2024-12-09

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan VU ,  Stephen TRINH ,  Stanley HONG ,  Anh LY ,  Steven LEMKE ,  Nha NGUYEN ,  Vipin TIWARI ,  Nhan DO

IPC: G11C16/34 ,  G06F3/06 ,  G06N3/063 ,  G06N3/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/10

Abstract: In one example, a method comprises determining a logarithmic slope factor for a selected analog non-volatile memory cell in an array of analog non-volatile memory cells while the selected analog non-volatile memory cell is operating in a sub-threshold region; storing the logarithmic slope factor; determining a linear slope factor for the selected analog non-volatile memory cell while the selected analog non-volatile memory cell is operating in a linear region; storing the linear slope factor; and utilizing one or more of the logarithmic slope factor and the linear slope factor when programming the selected analog non-volatile memory cell to a target current.

公开(公告)号：US20220398444A1

公开(公告)日：2022-12-15

申请号：US17893071

申请日：2022-08-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Thuan VU ,  Stephen TRINH ,  Stanley HONG ,  Anh LY ,  Steven LEMKE ,  Nha NGUYEN ,  Vipin TIWARI ,  Nhan DO

IPC: G06N3/063 ,  G06N3/04 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method comprises programming an analog neural non-volatile memory cell in an array to a target value representing one of N different values, where N is an integer; verifying that a value stored in the analog neural non-volatile memory cell is within an acceptable window of values around the target value; repeating the programming and verifying for each of the N values; and identifying the analog neural non-volatile memory cell as bad if any of the verifying indicates a value stored in the cell outside of the acceptable window of values around the target value.

公开(公告)号：US20140269098A1

公开(公告)日：2014-09-18

申请号：US13830207

申请日：2013-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van TRAN ,  Anh LY ,  Thuan VU ,  Hung Quoc NGUYEN

IPC: G11C16/12

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.

Abstract translation: 公开了用于编程高级纳米闪存单元的改进的方法和装置。