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    Self-Aligned Metal Gate for Multigate Device
    103.
    发明申请
    Self-Aligned Metal Gate for Multigate Device 有权

    公开(公告)号：US20210343600A1

    公开(公告)日：2021-11-04

    申请号：US17174109

    申请日：2021-02-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Ching-Wei Tsai ,  Shi Ning Ju ,  Jui-Chien Huang

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

    Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

    Self-Aligned Source/Drain Metal Contacts And Formation Thereof
    104.
    发明申请
    Self-Aligned Source/Drain Metal Contacts And Formation Thereof 有权

    公开(公告)号：US20210313448A1

    公开(公告)日：2021-10-07

    申请号：US16837883

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Pei-Hsun Wang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

    IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L21/764 ,  H01L21/8238

    Abstract: The present disclosure provides a method of semiconductor fabrication. The method includes forming a fin protruding from a substrate, the fin having a first sidewall and a second sidewall opposing the first sidewall; forming a sacrificial dielectric layer on the first and second sidewalls and a top surface of the fin; etching the sacrificial dielectric layer to remove the sacrificial dielectric layer from the second sidewall of the fin; forming a recess in the fin; growing an epitaxial source/drain (S/D) feature from the recess, the epitaxial S/D feature having a first sidewall and a second sidewall opposing the first sidewall, wherein the sacrificial dielectric layer covers the first sidewall of the epitaxial S/D feature; recessing the sacrificial dielectric layer, thereby exposing the first sidewall of the epitaxial S/D feature; and forming an S/D contact on the first sidewall of the epitaxial S/D feature.

    Nanosheet Device with Dipole Dielectric Layer and Methods of Forming the Same
    105.
    发明申请
    Nanosheet Device with Dipole Dielectric Layer and Methods of Forming the Same 有权

    公开(公告)号：US20210305400A1

    公开(公告)日：2021-09-30

    申请号：US16835759

    申请日：2020-03-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Chih-Hao Wang

    IPC: H01L29/51 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

    WORK FUNCTION DESIGN TO INCREASE DENSITY OF NANOSHEET DEVICES
    109.
    发明申请
    WORK FUNCTION DESIGN TO INCREASE DENSITY OF NANOSHEET DEVICES 有权

    公开(公告)号：US20210134794A1

    公开(公告)日：2021-05-06

    申请号：US16874907

    申请日：2020-05-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mao-Lin Huang ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Jia-Ni Yu ,  Lung-Kun Chu ,  Chung-Wei Hsu

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

    Abstract: In some embodiments, the present disclosure relates to an integrated chip including first, second, and third nanosheet field effect transistors (NSFETs) arranged over a substrate. The first NSFET has a first threshold voltage and includes first nanosheet channel structures embedded in a first gate electrode layer. The first nanosheet channel structures extend from a first source/drain region to a second source/drain region. The second NSFET has a second threshold voltage different than the first threshold voltage and includes second nanosheet channel structures embedded in a second gate electrode layer. The second nanosheet channel structures extend from a third source/drain region to a fourth source/drain region. The third NSFET has a third threshold voltage different than the second threshold voltage and includes third nanosheet channel structures embedded in a third gate electrode layer. The third nanosheet channel structures extend from a fifth source/drain region to a sixth source/drain region.

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