公开(公告)号：US08642430B2

公开(公告)日：2014-02-04

申请号：US13442683

申请日：2012-04-09

申请人： Stefan Flachowsky ,  Thilo Scheiper

发明人： Stefan Flachowsky ,  Thilo Scheiper

IPC分类号： H01L21/02 ,  H01L33/16 ,  H01L33/12

CPC分类号： H01L29/7847

摘要： Processes for preparing a stressed semiconductor wafer and processes for preparing devices including a stressed semiconductor wafer are provided herein. An exemplary process for preparing a stressed semiconductor wafer includes providing a semiconductor wafer of a first material having a first crystalline lattice constant. A stressed crystalline layer of a second material having a different lattice constant from the first material is pseudomorphically formed on a surface of the semiconductor wafer. A first via is etched through the stressed crystalline layer and at least partially into the semiconductor wafer to release stress in the stressed crystalline layer adjacent the first via, thereby transferring stress to the semiconductor wafer and forming a stressed region in the semiconductor wafer. The first via in the semiconductor wafer is filled with a first filler material to impede dissipation of stress in the semiconductor wafer.

摘要翻译： 本文提供了制备应力半导体晶片的工艺和用于制备包括应力半导体晶片的器件的工艺。 制备应力半导体晶片的示例性方法包括提供具有第一晶格常数的第一材料的半导体晶片。 具有与第一材料不同的晶格常数的第二材料的受应力结晶层在半导体晶片的表面上伪造形成。 第一通孔被蚀刻通过应力结晶层并且至少部分地进入半导体晶片以释放与第一通孔相邻的应力结晶层中的应力，从而将应力传递到半导体晶片并在半导体晶片中形成应力区域。 半导体晶片中的第一通孔填充有第一填充材料以阻止半导体晶片中的应力耗散。

公开(公告)号：US20130065367A1

公开(公告)日：2013-03-14

申请号：US13231470

申请日：2011-09-13

申请人： Stefan Flachowsky ,  Thilo Scheiper ,  Ricardo P. Mikalo

发明人： Stefan Flachowsky ,  Thilo Scheiper ,  Ricardo P. Mikalo

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864

摘要： In one example, a method disclosed herein includes the steps of forming gate electrode structures for a PMOS transistor and for an NMOS transistor, forming a first spacer proximate the gate electrode structures, after forming the first spacer, forming extension implant regions in the substrate for the transistors and after forming the extension implant regions, forming a second spacer proximate the first spacer for the PMOS transistor. This method also includes performing an etching process with the second spacer in place to define a plurality of cavities in the substrate proximate the gate structure for the PMOS transistor, removing the first and second spacers, forming a third spacer proximate the gate electrode structures of both of the transistors, and forming deep source/drain implant regions in the substrate for the transistors.

摘要翻译： 在一个示例中，本文公开的方法包括以下步骤：在形成第一间隔物之后，形成用于PMOS晶体管和用于NMOS晶体管的栅电极结构，形成靠近栅电极结构的第一间隔，在衬底中形成延伸注入区 晶体管和形成延伸注入区之后，形成靠近PMOS晶体管的第一间隔物的第二隔离层。 该方法还包括执行蚀刻工艺，其中第二间隔件就位以在衬底附近限定用于PMOS晶体管的栅极结构附近的多个空腔，去除第一和第二间隔物，形成邻近两个栅电极结构的第三间隔物 的晶体管，并且在用于晶体管的衬底中形成深源极/漏极注入区域。

公开(公告)号：US20130049164A1

公开(公告)日：2013-02-28

申请号：US13218589

申请日：2011-08-26

申请人： Peter Baars ,  Thilo Scheiper

发明人： Peter Baars ,  Thilo Scheiper

IPC分类号： H01L29/06 ,  H01L21/265

CPC分类号： H01L29/8611 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/822 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1207 ,  H01L27/127 ,  H01L29/66136

摘要： Disclosed herein are various methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes. In one example, the method includes performing a first angled ion implantation process to form a first doped region in a bulk layer of an SOI substrate for one of the anode or the diode and, after performing the first angled ion implantation process, performing a second angled ion implantation process to form a second doped region in the bulk layer of the SOI substrate for the other of the anode and the diode, wherein said first and second angled ion implantation process are performed through the same masking layer.

摘要翻译： 本文公开了通过进行角度离子注入工艺来形成衬底二极管的阳极和阴极的各种方法。 在一个示例中，该方法包括执行第一成角度离子注入工艺以在用于阳极或二极管之一的SOI衬底的体层中形成第一掺杂区域，并且在执行第一成角度离子注入工艺之后，执行第二 角度离子注入工艺，以在SOI衬底的体层中形成用于阳极和二极管中的另一个的第二掺杂区域，其中所述第一和第二成角度离子注入工艺通过相同的掩模层进行。

公开(公告)号：US20130032901A1

公开(公告)日：2013-02-07

申请号：US13204283

申请日：2011-08-05

申请人： Peter Javorka ,  Stefan Flachowsky ,  Thilo Scheiper

发明人： Peter Javorka ,  Stefan Flachowsky ,  Thilo Scheiper

IPC分类号： H01L21/336 ,  H01L29/78 ,  B82Y40/00

CPC分类号： H01L29/66507 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7845

摘要： Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.

公开(公告)号：US20120181655A1

公开(公告)日：2012-07-19

申请号：US13233762

申请日：2011-09-15

申请人： Thilo Scheiper ,  Stefan Flachowsky

发明人： Thilo Scheiper ,  Stefan Flachowsky

IPC分类号： H01L27/12 ,  H01L21/265

CPC分类号： H01L27/1203 ,  H01L27/1207

摘要： When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.

摘要翻译： 当形成复杂的SOI器件时，通过使用一个相同的注入掩模来形成衬底二极管和膜二极管，以确定相应阱区中的阱掺杂剂浓度。 因此，在进一步处理期间，可以独立于半导体层中的二极管的阱区实现任何晶体管元件的阱掺杂剂浓度。

公开(公告)号：US20120161238A1

公开(公告)日：2012-06-28

申请号：US13209057

申请日：2011-08-12

申请人： Thilo Scheiper ,  Andy Wei

发明人： Thilo Scheiper ,  Andy Wei

IPC分类号： H01L27/105 ,  H01L21/336

CPC分类号： H01L27/0886 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

摘要： Non-planar transistors, such as FinFETs, may be formed in a bulk configuration in the context of a replacement gate approach, wherein the semiconductor fins are formed during the replacement gate sequence. To this end, in some illustrative embodiments, a buried etch mask may be formed in an early manufacturing stage on the basis of superior process conditions.

摘要翻译： 在替代栅极方法的上下文中，非平面晶体管（例如FinFET）可以以体积形式形成，其中半导体鳍片在替换栅极序列期间形成。 为此，在一些说明性实施例中，可以在优良的工艺条件的基础上，在早期制造阶段中形成掩埋蚀刻掩模。

公开(公告)号：US20110291196A1

公开(公告)日：2011-12-01

申请号：US13017558

申请日：2011-01-31

申请人： Andy Wei ,  Vivien Schroeder ,  Thilo Scheiper ,  Thomas Werner ,  Johannes Groschopf

发明人： Andy Wei ,  Vivien Schroeder ,  Thilo Scheiper ,  Thomas Werner ,  Johannes Groschopf

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.

摘要翻译： 可以基于设置在掩模材料中的栅极开口或栅极沟槽形成体构造的三维晶体管。 因此，可以在由栅极开口限定的部分中的底层有源区域中有效地图案化自对准半导体鳍片，同时可以有效地屏蔽其中的栅极开口，其中将提供平面晶体管。 在图案化半导体鳍片并调整其有效高度之后，可以基于通常应用于平面晶体管和三维晶体管的工艺技术来继续进一步的处理。

公开(公告)号：US20130295767A1

公开(公告)日：2013-11-07

申请号：US13462246

申请日：2012-05-02

申请人： Thilo Scheiper ,  Peter Baars

发明人： Thilo Scheiper ,  Peter Baars

IPC分类号： H01L21/28 ,  H01L21/3065

CPC分类号： H01L21/823807 ,  H01L21/0206 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： When forming sophisticated transistors on the basis of a highly stressed dielectric material formed above a transistor, the stress transfer efficiency may be increased by reducing the size of the spacer structure of the gate electrode structure prior to depositing the highly stressed material. Prior to the deposition of the highly stressed material, an additional cleaning process may be implemented in order to reduce the presence of any metal contaminants, in particular in the vicinity of the gate electrode structure, which would otherwise result in an increased fringing capacitance.

摘要翻译： 当基于形成在晶体管上方的高应力电介质材料形成复杂的晶体管时，通过在沉积高应力材料之前减小栅电极结构的间隔结构的尺寸，可以增加应力传递效率。 在沉积高应力材料之前，可以实施额外的清洁工艺，以减少任何金属污染物的存在，特别是在栅电极结构附近，否则会导致增加的边缘电容。

公开(公告)号：US20130244388A1

公开(公告)日：2013-09-19

申请号：US13421604

申请日：2012-03-15

申请人： Thilo Scheiper ,  Stefan Flachowsky ,  Shesh Mani Pandey

发明人： Thilo Scheiper ,  Stefan Flachowsky ,  Shesh Mani Pandey

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/26586 ,  H01L21/823418 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a gate stack on a semiconductor substrate. In the method, a first halo implantation is performed on the semiconductor substrate with a first dose of dopant ions to form first halo regions therein. A second halo spacer is formed around the gate stack. Then a second halo implantation is performed on the semiconductor substrate with a second dose of dopant ions to form second halo regions therein.

摘要翻译： 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成栅叠层。 在该方法中，在第一剂量的掺杂剂离子的半导体衬底上进行第一晕圈注入，以在其中形成第一晕圈。 在栅堆叠周围形成第二晕环。 然后在第二剂量的掺杂剂离子的半导体衬底上进行第二晕圈注入，以在其中形成第二晕圈。

公开(公告)号：US08508001B2

公开(公告)日：2013-08-13

申请号：US13217792

申请日：2011-08-25

申请人： Steven Langdon ,  Stefan Flachowsky ,  Thilo Scheiper

发明人： Steven Langdon ,  Stefan Flachowsky ,  Thilo Scheiper

IPC分类号： H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L27/14 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78654

摘要： Disclosed herein is a semiconductor device that includes a semiconducting substrate and a work-function adjusting layer positioned at least partially in the semiconducting substrate, the work-function adjusting layer having a middle section, opposing ends and an end region located proximate each of said opposing ends and a gate electrode positioned above the work-function adjusting layer. Each of the end regions has a maximum thickness that is at least 25% greater than an average thickness of the middle section of the work-function adjusting layer.

摘要翻译： 本文公开了一种半导体器件，其包括半导体衬底和至少部分地位于半导体衬底中的功函数调整层，所述功函数调整层具有中间部分，相对端部和靠近所述相对的每一个的端部区域 端部和位于功函调整层上方的栅电极。 每个端部区域的最大厚度比工作功能调节层的中间部分的平均厚度大至少25％。