公开(公告)号：US08404550B2

公开(公告)日：2013-03-26

申请号：US12905383

申请日：2010-10-15

申请人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

发明人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66651

摘要： In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.

摘要翻译： 在包含高k金属栅电极结构的P沟道晶体管中，至少在阈值调节半导体材料（例如硅/锗材料）中可以通过掺入扩散阻挡物质获得优异的掺杂剂分布，例如 在形成阈值调节半导体材料之前。 因此，漏极和源极延伸区域可以被提供有高的掺杂剂浓度，以获得目标米勒电容，而不会导致低于阈值调节半导体材料的不适当的掺杂剂扩散，否则可能导致增加的漏电流和增加的穿孔风险 事件

公开(公告)号：US08349695B2

公开(公告)日：2013-01-08

申请号：US12848741

申请日：2010-08-02

申请人： Thilo Scheiper ,  Andy Wei ,  Martin Trentzsch

发明人： Thilo Scheiper ,  Andy Wei ,  Martin Trentzsch

IPC分类号： H01L23/336

CPC分类号： H01L21/823462 ,  H01L21/823857

摘要： In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided.

摘要翻译： 在复杂的制造技术中，工作功能和晶体管元件的阈值电压可以在早期制造阶段通过提供在高k电介质材料内调节物质的功函数来调节，其中栅极电介质材料具有基本上相同的空间分布 不同厚度。 在结合工作功能调整物质之后，可以通过选择性地形成额外的介电层来调节栅极电介质材料的最终厚度，使得栅电极结构的进一步图案化可以以与常规制造高度的相容性来实现 技术 因此，可以避免用于重新调整具有不同厚度栅极电介质材料的晶体管的阈值电压的非常复杂的工艺。

公开(公告)号：US20110266633A1

公开(公告)日：2011-11-03

申请号：US12963364

申请日：2010-12-08

申请人： Sven Beyer ,  Klaus Hempel ,  Roland Stejskal ,  Andy Wei ,  Thilo Scheiper ,  Andreas Kurz ,  Uwe Griebenow ,  Jan Hoentschel

发明人： Sven Beyer ,  Klaus Hempel ,  Roland Stejskal ,  Andy Wei ,  Thilo Scheiper ,  Andreas Kurz ,  Uwe Griebenow ,  Jan Hoentschel

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L23/5252 ,  H01L23/5256 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches.

摘要翻译： 在替代栅极方法中，可以在更换栅电极结构中的半导体材料时保留半导体材料或其非晶体管结构中的至少其重要部分，例如精密电阻器，电子熔丝等。 为此，可以至少在去除栅电极结构中的半导体材料之前提供适当的介电材料，而不需要对建立的替代栅极方法进行显着的修改。

公开(公告)号：US20090321836A1

公开(公告)日：2009-12-31

申请号：US12473610

申请日：2009-05-28

申请人： Andy Wei ,  Robert Mulfinger ,  Thilo Scheiper ,  Thorsten Kammler

发明人： Andy Wei ,  Robert Mulfinger ,  Thilo Scheiper ,  Thorsten Kammler

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7851

摘要： Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.

摘要翻译： 可以基于增强的掩模状态形成诸如FinFETS和三栅极晶体管的三维晶体管结构，从而能够在体半导体内以自对准的方式形成漏极和源极区域，鳍片和隔离结构 材料。 在定义基本的翅片结构之后，可以使用平面晶体管配置的高效制造技术，从而进一步提高三维晶体管配置的整体性能。

公开(公告)号：US08722500B2

公开(公告)日：2014-05-13

申请号：US13237688

申请日：2011-09-20

申请人： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

发明人： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/76897

摘要： Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.

摘要翻译： 提供了用于制造包括门到活动触点的集成电路的方法。 一种方法包括在替代栅极技术中处理IC，包括在虚拟栅极上形成伪栅极，侧壁间隔物以及金属硅化物触点到有源区域。 填充层被平坦化以暴露伪栅极并且去除虚拟栅极。 形成掩模，其具有覆盖通道区域的从其去除虚拟栅极的一部分的开口和相邻的金属硅化物接触的一部分。 蚀刻填充层和暴露在掩模开口中的侧壁间隔部分，以露出相邻的金属硅化物接触部分。 沉积覆盖沟道区域和暴露的金属硅化物接触的栅电极材料，并被平坦化以形成栅电极和栅极与金属的硅化物接触互连。

公开(公告)号：US08722498B2

公开(公告)日：2014-05-13

申请号：US13209057

申请日：2011-08-12

申请人： Thilo Scheiper ,  Andy Wei

发明人： Thilo Scheiper ,  Andy Wei

IPC分类号： H01L27/105

CPC分类号： H01L27/0886 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

摘要： Non-planar transistors, such as FinFETs, may be formed in a bulk configuration in the context of a replacement gate approach, wherein the semiconductor fins are formed during the replacement gate sequence. To this end, in some illustrative embodiments, a buried etch mask may be formed in an early manufacturing stage on the basis of superior process conditions.

摘要翻译： 在替代栅极方法的上下文中，非平面晶体管（例如FinFET）可以以体积形式形成，其中半导体鳍片在替换栅极序列期间形成。 为此，在一些说明性实施例中，可以在优良的工艺条件的基础上，在早期制造阶段中形成掩埋蚀刻掩模。

公开(公告)号：US08679924B2

公开(公告)日：2014-03-25

申请号：US13017558

申请日：2011-01-31

申请人： Andy Wei ,  Vivien Schroeder ,  Thilo Scheiper ,  Thomas Werner ,  Johannes Groschopf

发明人： Andy Wei ,  Vivien Schroeder ,  Thilo Scheiper ,  Thomas Werner ,  Johannes Groschopf

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.

摘要翻译： 可以基于设置在掩模材料中的栅极开口或栅极沟槽形成体构造的三维晶体管。 因此，可以在由栅极开口限定的部分中的底层有源区域中有效地图案化自对准半导体鳍片，同时可以有效地屏蔽其中的栅极开口，其中将提供平面晶体管。 在图案化半导体鳍片并调整其有效高度之后，可以基于通常应用于平面晶体管和三维晶体管的工艺技术来继续进一步的处理。

公开(公告)号：US20120280277A1

公开(公告)日：2012-11-08

申请号：US13548113

申请日：2012-07-12

申请人： Thilo Scheiper ,  Andy Wei ,  Sven Beyer

发明人： Thilo Scheiper ,  Andy Wei ,  Sven Beyer

IPC分类号： H01L29/78

CPC分类号： H01L21/28123 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions.

摘要翻译： 在复杂的晶体管元件中，可以通过使用非晶态的栅极材料来实现沿着晶体管宽度方向的增强的分布均匀性，从而减少沟道效应和线边缘粗糙度。 在复杂的高k金属栅极方法中，可以应用适当的顺序来避免在进行用于形成漏极和源极延伸区域和晕圈区域的关键注入工艺之前非晶态的变化。

公开(公告)号：US08241977B2

公开(公告)日：2012-08-14

申请号：US12692698

申请日：2010-01-25

申请人： Thilo Scheiper ,  Andy Wei ,  Sven Beyer

发明人： Thilo Scheiper ,  Andy Wei ,  Sven Beyer

IPC分类号： H01L21/8238

CPC分类号： H01L21/28123 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions.

摘要翻译： 在复杂的晶体管元件中，可以通过使用非晶态的栅极材料来实现沿着晶体管宽度方向的增强的分布均匀性，从而减少沟道效应和线边缘粗糙度。 在复杂的高k金属栅极方法中，可以应用适当的顺序来避免在进行用于形成漏极和源极延伸区域和晕圈区域的关键注入工艺之前非晶态的变化。

公开(公告)号：US20120196425A1

公开(公告)日：2012-08-02

申请号：US13354613

申请日：2012-01-20

申请人： Thilo Scheiper ,  Andy Wei ,  Stefan Flachowsky ,  Jan Hoentschel

发明人： Thilo Scheiper ,  Andy Wei ,  Stefan Flachowsky ,  Jan Hoentschel

IPC分类号： H01L21/762 ,  H01L21/28

CPC分类号： H01L29/785 ,  H01L21/823828 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66795

摘要： When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, superior process uniformity may be achieved by implementing at least one planarization process after the deposition of the placeholder material, such as the polysilicon material, and prior to actually patterning the gate electrode structures.

摘要翻译： 当基于替代栅极方法形成复杂的高k金属栅电极结构时，可以通过在诸如多晶硅材料的占位符材料的沉积之后实施至少一个平坦化工艺，并且在实际上 图案化栅电极结构。