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180 条记录 (耗时 0.033 秒)

    Semiconductor memory device
    102.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060291279A1

    公开(公告)日：2006-12-28

    申请号：US11473402

    申请日：2006-06-24

    申请人： Chang-Ho Shin ,  Jong-Hyun Choi

    发明人： Chang-Ho Shin ,  Jong-Hyun Choi

    IPC分类号： G11C11/34

    CPC分类号： G11C5/145 ,  G11C5/147

    摘要： A semiconductor memory device includes a cell array internal voltage generating circuit for generating cell array reference voltage and a cell array power voltage from a first external power voltage, a peripheral circuit internal voltage generating circuit for generating a peripheral circuit reference voltage and a peripheral circuit power voltage from the first external power voltage, and a voltage boosting circuit power voltage generating circuit for generating a voltage boosting circuit reference voltage and a voltage boosting circuit power voltage from a second external power voltage.

    摘要翻译： 一种半导体存储器件，包括用于从第一外部电源电压产生单元阵列参考电压和单元阵列电源电压的单元阵列内部电压产生电路，用于产生外围电路参考电压的外围电路内部电压产生电路和外围电路电源 来自第一外部电源电压的电压，以及用于从第二外部电源电压产生升压电路参考电压和升压电路电源电压的升压电路电源电压产生电路。

    Fuse arrangement and integrated circuit device using the same
    104.
    发明授权
    Fuse arrangement and integrated circuit device using the same 失效
    保险丝布置和集成电路器件使用相同

    公开(公告)号：US07057217B2

    公开(公告)日：2006-06-06

    申请号：US10672035

    申请日：2003-09-26

    申请人： Sang-Seok Kang ,  Jong-Hyun Choi ,  Sang-Ki Hwang

    发明人： Sang-Seok Kang ,  Jong-Hyun Choi ,  Sang-Ki Hwang

    IPC分类号： H01L27/10

    CPC分类号： G11C17/143 ,  G11C29/785 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse circuit according to the present invention includes first and second fuses, each of which has a first end and a second end. The first and second ends of the first fuse are connected in a straight line. The first end of the second fuse is spaced by a first interval from the first end of the first fuse, and the second end thereof is spaced by a second interval from the second end of the first fuse. The first ends of the first and second fuses have the same widths as those of the second ends thereof. Alternatively, the first ends of the first and second fuses have narrower widths that those of the second ends thereof.

    摘要翻译： 根据本发明的熔丝电路包括第一和第二熔丝，每个熔丝具有第一端和第二端。 第一保险丝的第一端和第二端以直线连接。 第二保险丝的第一端与第一保险丝的第一端隔开第一间隔，并且第二保险丝的第二端与第一保险丝的第二端隔开第二间隔。 第一和第二熔断器的第一端具有与其第二端相同的宽度。 或者，第一和第二熔断器的第一端的宽度比第二端的宽度窄。

    Wafer burn-in test circuit and method for testing a semiconductor memory device
    106.
    发明授权
    Wafer burn-in test circuit and method for testing a semiconductor memory device 有权
    晶圆老化测试电路和半导体存储器件测试方法

    公开(公告)号：US06266286B1

    公开(公告)日：2001-07-24

    申请号：US09457909

    申请日：1999-12-08

    申请人： Soo-In Cho ,  Jong-Hyun Choi

    发明人： Soo-In Cho ,  Jong-Hyun Choi

    IPC分类号： G11C700

    CPC分类号： G11C29/025 ,  G11C11/401 ,  G11C29/006 ,  G11C29/02 ,  G11C29/50

    摘要： A wafer burn-in test circuit of a semiconductor memory device having a plurality of memory cells arranged in a row/column matrix, is provided, including:a sub word line driver connected to first and second word line groups each connected to true cells and complement cells forming the memory cells, and responding to a predecoded low address; and first and second power lines respectively supplying power to the corresponding first and second power line groups by a switching operation of the sub word line driver, wherein a ground power source is applied to the first and second power lines during a normal operation, and the ground power source and a step-up power source are alternately applied to the first and second power lines during a wafer burn-in test operation.

    摘要翻译： 提供了具有以行/列矩阵排列的多个存储单元的半导体存储器件的晶片老化测试电路，包括：连接到每个连接到真实单元的第一和第二字线组的子字线驱动器，以及 形成存储器单元的补码单元，以及对预解码的低地址的响应; 以及分别通过子字线驱动器的切换操作向对应的第一和第二电力线组提供电力的第一和第二电力线，其中在正常操作期间将地电源施加到第一和第二电力线，并且 接地电源和升压电源在晶片老化测试操作期间交替施加到第一和第二电源线。

    Word line loading compensating circuit of semiconductor memory device
    107.
    发明授权
    Word line loading compensating circuit of semiconductor memory device 失效
    半导体存储器件的字线负载补偿电路

    公开(公告)号：US5504715A

    公开(公告)日：1996-04-02

    申请号：US343949

    申请日：1994-11-17

    申请人： Yeong-Taek Lee ,  Jong-Hyun Choi

    发明人： Yeong-Taek Lee ,  Jong-Hyun Choi

    IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/00

    CPC分类号： G11C8/08

    摘要： A word line loading compensating circuit compensates a word line boosted voltage level changed in accordance with a word line loading. A word line boosting circuit outputs a word line boosted voltage boosted over a power supply voltage input from the exterior of a chip, so as to boost a voltage of the word line connected to the memory cell array. A row decoder is connected to the word line boosted voltage output from the word line boosting circuit and selects a memory cell from an array of memory cells in correspondence with a predetermined row address signal. A capacitor connected between the word line boosted voltage and the row decoder stores a charge from the word line boosted voltage. A variable connecting device connects the word line boosted voltage to the capacitor before the word line boosted voltage reaches a saturation level, and cuts off the word line boosted voltage from the capacitor after the word line boosted voltage reaches the saturation level. A delay device inputs the word line boosted voltage, delays the input word line boosted voltage during the arrival time of the saturation level, and generates a delay output signal which controls the variable connecting device. A discharging device is controlled by the delay output signal and discharges the charge stored in the capacitor to ground after the word line boosted voltage reaches the saturation level.

    摘要翻译： 字线负载补偿电路补偿根据字线负载而改变的字线升压电压电平。 字线升压电路输出从芯片外部输入的电源电压升压的字线升压电压，以提高连接到存储单元阵列的字线的电压。 行解码器连接到从字线升压电路输出的字线升压电压，并根据预定行地址信号从存储器单元阵列中选择存储单元。 连接在字线升压电压和行解码器之间的电容器存储来自字线升压电压的电荷。 可变连接装置在字线升压电压达到饱和电平之前将字线升压电压连接到电容器，并且在字线升压电压达到饱和电平后，切断来自电容器的字线升压电压。 延迟装置输入字线升压电压，在饱和电平到达时延迟输入字线升压电压，并产生控制可变连接装置的延迟输出信号。 放电装置由延迟输出信号控制，并且在字线升压电压达到饱和电平后，将存储在电容器中的电荷放电到地。

    Organic light emitting display device
    108.
    发明授权
    Organic light emitting display device 有权
    有机发光显示装置

    公开(公告)号：US09342176B2

    公开(公告)日：2016-05-17

    申请号：US12409375

    申请日：2009-03-23

    申请人： Young-Dae Kim ,  Jong-Hyun Choi ,  Choong-Youl Im ,  Il-Jeong Lee

    发明人： Young-Dae Kim ,  Jong-Hyun Choi ,  Choong-Youl Im ,  Il-Jeong Lee

    IPC分类号： G09G3/30 ,  G06F3/041 ,  G06F3/044 ,  H01L27/32

    CPC分类号： G06F3/0412 ,  G06F3/044 ,  G06F2203/04111 ,  H01L27/323 ,  H01L27/3244 ,  H01L2251/308 ,  H01L2251/5338 ,  H01L2251/5392

    摘要： An organic light emitting display device having an electrostatic capacitive type touch panel function with reduced thickness and improved luminance. A display panel of the organic light emitting display device includes a substrate, a display unit having a plurality of pixels on the substrate, and a touch sensing unit on the display unit. The touch sensing unit includes an encapsulation substrate and a capacitive pattern layer on a side of the encapsulation substrate facing the display unit. The capacitive pattern layer has a plurality of openings corresponding in position to the plurality of pixels.

    摘要翻译： 一种具有静电电容型触摸面板功能的有机发光显示装置，具有减小的厚度和改善的亮度。 有机发光显示装置的显示面板包括基板，在基板上具有多个像素的显示单元和显示单元上的触摸感测单元。 触摸感测单元包括封装基板和位于封装基板的面向显示单元的一侧的电容图案层。 电容图案层具有对应于多个像素的位置的多个开口。