公开(公告)号：US07973317B2

公开(公告)日：2011-07-05

申请号：US12752192

申请日：2010-04-01

Applicant: Yu-Cheng Chen ,  Chen-Yueh Li

Inventor： Yu-Cheng Chen ,  Chen-Yueh Li

IPC: H01L27/14

CPC classification number: H01L27/124 ,  H01L27/1255

Abstract: A method for fabricating an array substrate for a liquid crystal display (LCD) is provided. A semiconductor layer and a transparent lower electrode formed on a substrate is provided and covered by a first dielectric layer serving as a gate dielectric layer and a capacitor dielectric layer. A gate electrode and an upper electrode comprising a transparent electrode portion and a metal electrode portion are formed on the first dielectric layer and covered by a second dielectric layer. A source/drain electrode, a planarization layer, and a pixel electrode are sequentially formed on the second dielectric layer, in which the source/drain electrode is electrically connected to the semiconductor layer through the first and second dielectric layers and the pixel electrode is electrically connected to the source/drain electrode through the planarization layer. An array substrate for an LCD is also disclosed.

Abstract translation: 提供一种用于制造液晶显示器（LCD）阵列基板的方法。 提供形成在基板上的半导体层和透明下电极，并被用作栅极介电层和电容器电介质层的第一介电层覆盖。 包括透明电极部分和金属电极部分的栅电极和上电极形成在第一电介质层上并被第二电介质层覆盖。 源极/漏极，平坦化层和像素电极依次形成在第二电介质层上，其中源极/漏极通过第一和第二电介质层电连接到半导体层，并且像素电极是电 通过平坦化层与源极/漏极连接。 还公开了一种用于LCD的阵列基板。

公开(公告)号：US07939964B2

公开(公告)日：2011-05-10

申请号：US11882538

申请日：2007-08-02

Applicant: Yu-Cheng Chen

Inventor： Yu-Cheng Chen

IPC: H02J5/00 ,  H02J1/00

CPC classification number: H02M1/36 ,  H02M2001/008 ,  H02M2001/009 ,  Y10T307/25 ,  Y10T307/406 ,  Y10T307/461 ,  Y10T307/469 ,  Y10T307/484

Abstract: A modularized power supply switch control structure aims to control a main power system of a power supply. The main power system includes at least one high voltage output unit at a high voltage output end and one low voltage output unit at a rear low voltage output end. A control unit is connected to the high voltage output unit and the low voltage output unit to control start/stop time series of the high voltage output unit and the low voltage output unit so that the high voltage output unit and the low voltage output unit can be started asynchronously. Thus the power supply can output a start voltage at the start instant to meet load requirement. A plurality of power output modules deliver output asynchronously. Hence output current or voltage surge at the start instant can be improved.

Abstract translation: 模块化电源开关控制结构旨在控制电源的主电源系统。 主电源系统包括高压输出端的至少一个高压输出单元和后低压输出端的一个低电压输出单元。 控制单元连接到高压输出单元和低压输出单元，以控制高压输出单元和低压输出单元的启动/停止时间序列，使得高压输出单元和低压输出单元可以 可以异步启动 因此，电源可以在启动时输出启动电压以满足负载要求。 多个功率输出模块异步传送输出。 因此，可以提高起动时的输出电流或电压浪涌。

公开(公告)号：US20110080388A1

公开(公告)日：2011-04-07

申请号：US12629884

申请日：2009-12-03

Applicant: Wan-Yu Lo ,  Tsan-Chun Wang ,  Yu-Cheng Chen ,  Maw-Song Chen

Inventor： Wan-Yu Lo ,  Tsan-Chun Wang ,  Yu-Cheng Chen ,  Maw-Song Chen

IPC: G09G5/00 ,  G09G3/20

CPC classification number: G09G3/20 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0281

Abstract: A display panel including an active device array substrate, an opposite substrate and a display medium is provided. The active device array substrate includes a substrate, scan lines, data lines, pixel units, and data signal transmission lines. The scan lines and data lines define a plurality of pixel regions on the substrate. Each pixel unit is disposed within one of the pixel regions respectively, and each pixel unit includes a plurality of sub-pixel units. The sub-pixel units within the same pixel unit are electrically connected with the same data line, and each sub-pixel unit within the same pixel unit is electrically connected with one of the scan lines respectively. Each data signal transmission line is electrically connected with one of the data lines, and an extending direction of the data signal transmission line is substantially parallel with an extending direction of the scan lines.

Abstract translation: 提供了包括有源器件阵列衬底，相对衬底和显示介质的显示面板。 有源器件阵列衬底包括衬底，扫描线，数据线，像素单元和数据信号传输线。 扫描线和数据线在衬底上限定多个像素区域。 每个像素单元分别设置在一个像素区域内，并且每个像素单元包括多个子像素单元。 相同像素单元内的子像素单元与相同的数据线电连接，并且相同像素单元内的每个子像素单元分别与扫描线之一电连接。 每个数据信号传输线与数据线之一电连接，并且数据信号传输线的延伸方向与扫描线的延伸方向基本平行。

公开(公告)号：US20100315583A1

公开(公告)日：2010-12-16

申请号：US12788876

申请日：2010-05-27

Applicant: Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

Inventor： Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

IPC: G02F1/1343 ,  H01L21/84

CPC classification number: G02F1/136209 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2201/40 ,  H01L27/1248 ,  H01L27/1255

Abstract: This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.

Abstract translation: 本发明在一个方面涉及像素结构。 在一个实施例中，像素结构包括形成在衬底上的扫描线和形成在限定像素区域的衬底上的数据线，形成在衬底上的像素区域内的开关，形成在开关上的屏蔽电极，有机平面 形成在日期线和像素区域上并且与屏蔽电极不重叠的像素电极，以及具有从第一部分延伸的第一部分和第二部分的像素电极，并且形成在屏蔽电极和平面有机层的上方 像素区域，其中第一部分与屏蔽电极重叠以便在其间限定存储电容器，并且第二部分覆盖平面有机层并且不与数据线重叠。

公开(公告)号：US07824970B2

公开(公告)日：2010-11-02

申请号：US12781135

申请日：2010-05-17

Applicant: Yu-Cheng Chen

Inventor： Yu-Cheng Chen

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L27/124 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2201/40

Abstract: A semiconductor structure and a method for manufacturing the same are provided. Compared to conventional structures of thin film transistors, the structure of the present invention uses a patterned first metal layer as a data line, and a patterned second metal layer as a gate line. In a thin film transistor, a gate is also located in the patterned first metal layer, and is electrically connected to the gate line located in the patterned second metal layer through a contact hole. A source and a drain of the thin film transistor are electrically connected to the data line through a contact hole. The structure of the present invention increases a storage capacitance and an aperture ratio.

公开(公告)号：US20100267177A1

公开(公告)日：2010-10-21

申请号：US12559506

申请日：2009-09-15

Applicant: Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Ching-Chieh Shih ,  An-Thung Cho

Inventor： Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Ching-Chieh Shih ,  An-Thung Cho

IPC: H01L21/28

CPC classification number: H01L27/1288 ,  H01L27/1214

Abstract: A method for fabricating an active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is formed on the display area of the substrate. A gate insulator is formed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are formed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then formed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is formed on the passivation layer.

Abstract translation: 提供一种用于制造有源器件阵列衬底的方法。 首先，提供具有显示区域和感测区域的基板。 然后，在基板的显示区域上形成第一图案化导体层。 在基板上形成栅极绝缘体。 图案化的半导体层，第二图案化导体层和图案化的光敏介电层形成在栅极绝缘体上，其中第二图案化导体层包括源电极，漏电极和下电极，图案化的感光介电层覆盖第二 图案化导体层包括设置在源电极和漏电极上的界面保护层和设置在下电极上的感光层。 然后在衬底上形成钝化层。 之后，在钝化层上形成包括像素电极和上电极的第三图案化导体层。

公开(公告)号：US20100188378A1

公开(公告)日：2010-07-29

申请号：US12498323

申请日：2009-07-06

Applicant: Yi-Chen Chiang ,  Yu-Cheng Chen

Inventor： Yi-Chen Chiang ,  Yu-Cheng Chen

IPC: G06F3/038

CPC classification number: G09G3/3648 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0281

Abstract: A display device includes a substrate, gate lines, data lines, gate tracking lines, and dummy gate tracking lines. The gate lines and the data lines are arranged perpendicularly. Each gate tracking line is disposed between one parts of two adjacent data lines, and substantially parallel to the data lines. Each dummy gate tracking line is electrically disconnected to the gate lines, disposed between other parts of two adjacent data lines, and substantially parallel to the data lines.

Abstract translation: 显示装置包括基板，栅极线，数据线，栅极跟踪线和虚拟栅极跟踪线。 栅极线和数据线垂直布置。 每个栅极跟踪线设置在两个相邻数据线的一部分之间，并且基本上平行于数据线。 每个虚拟栅极跟踪线与两条相邻数据线的其它部分之间的栅极线电气断开，并且基本上平行于数据线。

公开(公告)号：US20100165920A1

公开(公告)日：2010-07-01

申请号：US12478841

申请日：2009-06-05

Applicant: Yu-Cheng Chen

Inventor： Yu-Cheng Chen

IPC: H04W40/00

CPC classification number: H04W72/1231 ,  H04L69/16 ,  H04L69/163 ,  H04W72/1273 ,  H04W80/06

Abstract: The invention discloses a method for boosting the downlink transmission rate to a mobile station by a processing unit thereof, including the steps of requesting a base station for a bandwidth amount for transmission of at least one un-generated acknowledgement (ACK) packet, generating the ACK packet or packets, and instructing an RF module to transmit the ACK packet or packets to the base station following a notification from the base station indicating that the requested bandwidth amount has been allocated.

Abstract translation: 本发明公开了一种通过其处理单元来提升对移动台的下行传输速率的方法，包括以下步骤：向基站请求用于发送至少一个未生成的确认（ACK）分组的带宽量，产生 ACK分组或分组，并且指示RF模块在从基站发出的指​​示已经分配了请求的带宽量的通知之后向基站发送ACK分组或分组。

公开(公告)号：US07745243B2

公开(公告)日：2010-06-29

申请号：US12416934

申请日：2009-04-02

Applicant: Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Kun-Chih Lin

Inventor： Yu-Cheng Chen ,  Chen-Yueh Li ,  Ching-Sang Chuang ,  Kun-Chih Lin

IPC: H01L21/8232

CPC classification number: G02F1/133555 ,  G02F2001/136231

Abstract: A forming method of the present invention includes forming a first patterned conductive layer, which includes a transparent conductive layer and a metal layer stacked together on a substrate, where the first patterned conductive layer functions as gate lines, gate electrodes, common lines and predetermined transparent pixel electrode structures; and forming a second patterned conductive layer on the substrate. The second patterned conductive layer includes data lines and reflective pixel electrodes, and be directly connected to doping regions, such as source regions/drain regions. According to the forming method of the present invention, pixel structures of a transflective liquid crystal display device can be formed through five mask processes. Therefore, the manufacturing process of the transflective liquid crystal display device is effectively simplified, so the product yield is improved and the cost can be reduced.

Abstract translation: 本发明的形成方法包括形成第一图案化导电层，其包括在基板上堆叠在一起的透明导电层和金属层，其中第一图案化导电层用作栅极线，栅电极，共同线和预定透明 像素电极结构; 以及在所述衬底上形成第二图案化导电层。 第二图案化导电层包括数据线和反射像素电极，并且直接连接到诸如源极区/漏极区的掺杂区。 根据本发明的形成方法，可以通过五个掩模工艺形成半透射型液晶显示装置的像素结构。 因此，有效地简化了半透射型液晶显示装置的制造工艺，从而提高了产品成品率，降低了成本。

公开(公告)号：US07738049B2

公开(公告)日：2010-06-15

申请号：US12121772

申请日：2008-05-15

Applicant: Yu-Cheng Chen

Inventor： Yu-Cheng Chen

IPC: G02F1/136

CPC classification number: G02F1/136286 ,  G02F1/133555 ,  G02F1/136227 ,  G02F2001/13606 ,  G02F2201/50 ,  H01L27/124 ,  H01L27/1255

Abstract: An active device array substrate including a substrate, a plurality of semiconductor patterns, a gate insulator layer, a first patterned conductive layer, a dielectric layer, a plurality of transparent electrodes, a passivation layer, and a second patterned conductive layer is provided. The semiconductor patterns are disposed on the substrate. The gate insulator layer is disposed on the substrate to cover the semiconductor patterns. The first patterned conductive layer disposed on the gate insulator layer includes a plurality of scan lines, a plurality of gate electrodes disposed on each semiconductor pattern and connected with the scan lines, and a plurality of common electrodes disposed between the scan lines. The dielectric layer is disposed on the gate insulator layer to cover the first patterned conductive layer. The transparent electrodes are disposed on the dielectric layer. The passivation layer is disposed on parts of the dielectric layer to expose the transparent electrodes.

Abstract translation: 提供了包括衬底，多个半导体图案，栅极绝缘体层，第一图案化导电层，电介质层，多个透明电极，钝化层和第二图案化导电层的有源器件阵列衬底。 半导体图案设置在基板上。 栅极绝缘体层设置在衬底上以覆盖半导体图案。 设置在栅极绝缘体层上的第一图案化导电层包括多个扫描线，设置在每个半导体图案上并与扫描线连接的多个栅电极，以及设置在扫描线之间的多个公共电极。 电介质层设置在栅极绝缘体层上以覆盖第一图案化导电层。 透明电极设置在电介质层上。 钝化层设置在电介质层的一部分上以露出透明电极。