公开(公告)号：US06978330B1

公开(公告)日：2005-12-20

申请号：US10117780

申请日：2002-04-04

Applicant: Alexander Joffe ,  Asad Khamisy

Inventor： Alexander Joffe ,  Asad Khamisy

IPC: G06F1/00 ,  G06F9/46

CPC classification number: G06F9/526

Abstract: Logic (also called “re-ordering semaphore”) issues semaphore grants to access a shared resource in an order different from the order in which semaphore requests for accessing the shared resource are received. The re-ordering semaphore needs to receive a semaphore release between any two semaphore grants. There is no limit on the duration between a semaphore grant and a semaphore release, so that a task that receives a semaphore grant can use the shared resource for any length of time. In one embodiment, each request is associated with a number indicative of the order in which grants are to be issued, and the re-ordering semaphore uses this number in deciding which request is to be granted. The number can be a sequence number that is indicative of the order of arrival of packets that generated the requests.

Abstract translation: 逻辑（也称为“重新排序信号量”）发出信号量授权以不同于接收到访问共享资源的信号量请求的顺序来访问共享资源。 重新排序信号量需要在任何两个信号量授权之间接收信号量释放。 在信号量授权和信号量发布之间的持续时间没有限制，因此接收信号量授权的任务可以使用共享资源任何时间长度。 在一个实施例中，每个请求与指示要发放授权的顺序的数字相关联，并且重新排序信号量在决定要授予哪个请求时使用该数字。 该数字可以是指示生成请求的分组的到达顺序的序列号。

公开(公告)号：US06938132B1

公开(公告)日：2005-08-30

申请号：US10117779

申请日：2002-04-04

Applicant: Alexander Joffe ,  Asad Khamisy

Inventor： Alexander Joffe ,  Asad Khamisy

IPC: G06F9/38 ,  G06F12/00

CPC classification number: G06F9/3879 ,  G06F9/3824 ,  G06F9/3851

Abstract: A co-processor (also called “memory co-processor”) provides an interface to a memory, by executing instructions on data held in the memory. The co-processor uses a specified address to fetch data from memory, performs a specified instruction (such as incrementing a counter or policing) on the data to obtain modified data, and writes the modified data back to memory at the same address. Depending on the embodiment, the memory co-processor may include a first buffer for holding instructions that may be received back to back, in successive clock cycles. Instead of or in addition to the first buffer, the memory co-processor may include a second buffer for holding data to be written to memory back to back, in successive clock cycles. In some embodiments, the memory co-processor also receives (and maintains in local storage) the identity of a task that generates the specified instruction, so that the same cask may be awakened after the instruction has been executed.

Abstract translation: 协处理器（也称为“存储器协处理器”）通过对存储器中保存的数据执行指令来向存储器提供接口。 协处理器使用指定的地址从存储器中取出数据，对数据执行指定的指令（例如增加计数器或监管）以获得修改的数据，并将修改的数据写回到同一地址的存储器。 根据实施例，存储器协处理器可以包括用于保持在连续的时钟周期中可以背靠背地接收的指令的第一缓冲器。 存储器协处理器代替或除了第一缓冲器之外，可以包括用于在连续的时钟周期内将要被写回存储的数据保存在第二缓冲器中。 在一些实施例中，存储器协处理器还接收（并维护本地存储器）生成指定指令的任务的身份，从而在执行指令之后可以唤醒相同的桶。

公开(公告)号：US06912667B1

公开(公告)日：2005-06-28

申请号：US10094247

申请日：2002-03-08

Applicant: Andrew Mark Player ,  Eric Minghorng Su

Inventor： Andrew Mark Player ,  Eric Minghorng Su

IPC: G06F11/10 ,  H04J3/14 ,  H04L1/24

CPC classification number: H04L1/24 ,  H04J3/14 ,  H04J2203/006

Abstract: A system and method are provided for transporting FTFL messages in a G.709 network-connected simplex device. The method comprises: receiving messages from a first source in a digital wrapper frame format with overhead bytes in every frame; recovering FTFL information from the received message overhead bytes; and, selectively supplying modified FTFL information for transmit message overhead bytes to the first source. Recovering FTFL information from the received message overhead bytes includes recovering a 256 byte FTFL message, including a 128-byte forward message and a 128-byte backward message. Selectively supplying modified FTFL information for transmit message overhead bytes to the first source includes the substeps of: examining the received messages to determine errors; generating a backward message to report the determined errors; overwriting the received backward message with the generated backward message to create the modified FTFL information; and, in response to overwriting the received backward message with the generated backward message, sending a FTFL_status_out signal. Then, the method further comprises: transmitting messages to the first source with the modified FTFL information in response to the FTFL_status_out signal.

Abstract translation: 提供了一种在G.709网络连接的单工设备中传送FTFL消息的系统和方法。 该方法包括：以数字包装帧格式接收来自第一源的消息，每帧中开销字节; 从接收的消息开销字节恢复FTFL信息; 并且向第一源选择性地提供用于发送消息开销字节的修改的FTFL信息。 从接收到的消息开销字节恢复FTFL信息包括恢复包括128字节转发消息和128字节反向消息的256字节FTFL消息。 将传输消息开销字节的修改的FTFL信息选择性地提供给第一源包括以下子步骤：检查接收到的消息以确定错误; 产生反向消息来报告确定的错误; 用生成的反向消息覆盖所接收的反向消息以创建修改的FTFL信息; 并且响应于利用生成的反向消息重写所接收的反向消息，发送FTFL_status_out信号。 然后，该方法还包括：响应于FTFL_status_out信号，将具有修改的FTFL信息的消息发送到第一源。

公开(公告)号：US06897700B1

公开(公告)日：2005-05-24

申请号：US10394845

申请日：2003-03-21

Applicant: Wei Fu ,  Joseph James Balardeta

Inventor： Wei Fu ,  Joseph James Balardeta

IPC: H03F3/45 ,  H03L5/00

CPC classification number: H03F3/45968 ,  H03F3/45744 ,  H03F2203/45366 ,  H03F2203/45544 ,  H03F2203/45598

Abstract: A high speed, high sensitivity post amplifier as described herein includes a digitally-controlled DC offset cancellation feature. The amplifier circuit is configured to provide DC offset voltage levels in response to a digital control signal, where the digital control signal is generated based upon a data error metric such as bit error rate. The AC signal path and the DC offset adjustment signal path in the amplifier circuit are separated to facilitate operation with normal power supply voltages, and to achieve low power operation.

Abstract translation: 如本文所述的高速，高灵敏度后置放大器包括数字控制的DC偏移消除特征。 放大器电路被配置为响应于数字控制信号提供DC偏移电压电平，其中基于诸如误码率的数据误差度量而产生数字控制信号。 放大器电路中的交流信号路径和直流偏移调整信号路径被分离以便于以正常的电源电压进行操作，并实现低功率操作。

公开(公告)号：US06873605B1

公开(公告)日：2005-03-29

申请号：US09753183

申请日：2001-01-02

Applicant: George Beshara Bendak ,  Alan Michael Sorgi

Inventor： George Beshara Bendak ,  Alan Michael Sorgi

IPC: H04B1/44 ,  H04J3/08 ,  H04J3/14

CPC classification number: H04J3/085 ,  H04J3/14

Abstract: A system and method is provided which describe a self-healing bidirectional lines switch ring (BLSR) communication node. Two interconnected relay elements, having default and duplex input and output ports, enable bidirectional communications through a node. In the event of a ring failure, the relays can be enabled to return communications to a source node so that the ring remains unbroken.

Abstract translation: 提供了一种描述自修复双向线路交换环（BLSR）通信节点的系统和方法。 两个互连的继电器元件，具有默认和双工输入和输出端口，实现了通过节点的双向通信。 在环路故障的情况下，可以使继电器返回到源节点的通信，使得环保持不间断。

公开(公告)号：US6121804A

公开(公告)日：2000-09-19

申请号：US140840

申请日：1998-08-27

Applicant: Thomas Clark Bryan ,  Allen Carl Merrill ,  Wei Fu

Inventor： Thomas Clark Bryan ,  Allen Carl Merrill ,  Wei Fu

IPC: H03D13/00 ,  H03L7/089 ,  H04L7/033 ,  H03L7/00

CPC classification number: H04L7/033 ,  H03D13/003 ,  H03L7/089

Abstract: A complementary metal-oxide semiconductor (CMOS) integrated circuit that includes a clock recovery circuit. The clock recovery circuit automatically properly aligns a clock with data. A latch is used to perform the function of a flip-flop. Because the flip flop is essentially two latches, using the latch rather than the flip flop results in a circuit having one less latch. Consequently, the circuit has less propagation delay, which permits higher frequency operation. Use of the latch also reduces the load on the clock and saves power. Additionally, the clock recovery circuit uses differential logic, which decreases noise sensitivity and allows higher frequency operation.

Abstract translation: 一种互补金属氧化物半导体（CMOS）集成电路，其包括时钟恢复电路。 时钟恢复电路自动将时钟与数据正确对齐。 锁存器用于执行触发器的功能。 因为触发器本质上是两个锁存器，所以使用锁存器而不是触发器导致具有少一个锁存器的电路。 因此，电路具有较少的传播延迟，这允许更高频率的操作。 使用锁存器还可以减少时钟上的负载并节省电力。 此外，时钟恢复电路使用差分逻辑，这降低了噪声灵敏度，并允许更高频率的操作。

公开(公告)号：US5969590A

公开(公告)日：1999-10-19

申请号：US910456

申请日：1997-08-05

Applicant: German R. Gutierrez

Inventor： German R. Gutierrez

IPC: H01F27/28 ,  H01F5/00

CPC classification number: H01F27/2804

Abstract: An integrated circuit transformer includes multiple metal layers in the structure of an integrated circuit in which are formed a first spiral inductor and a second spiral inductor. The first spiral inductor is aligned with and beneath the second spiral inductor such that the first spiral inductor acts to magnetically excite the second spiral inductor, while shielding it from resistance losses to the substrate.

Abstract translation: 集成电路变压器包括在其中形成有第一螺旋电感器和第二螺旋电感器的集成电路的结构中的多个金属层。 第一螺旋电感器与第二螺旋电感器对准并且在第二螺旋电感器下方，使得第一螺旋电感器用于磁性地激励第二螺旋电感器，同时屏蔽其抵抗衬底的电阻损耗。

公开(公告)号：US5914621A

公开(公告)日：1999-06-22

申请号：US19521

申请日：1998-02-05

Applicant: Bruce Harrison Coy

Inventor： Bruce Harrison Coy

IPC: H03K4/06 ,  H03K4/90

CPC classification number: H03K4/90 ,  H03K4/06

Abstract: A ramp circuit repeatedly generates a substantially linear ramp signal. Ramp switch junction capacitance that otherwise causes a nonlinear output is compensated to improve signal linearity and enable faster retriggering. The ramp includes an output transistor, with its output coupled to a current source and a charge storage device. The output charge storage device charges when the transistor is on. When the transistor is turned off, the output charge storage device discharges, resulting in the changing ramp signal. The output transistor inherently includes a junction capacitance, which causes a nonlinearity in the discharge of the charge storage device. This nonlinearity appears as a quick drop in the ramp signal relative to the slower rate of steady-state decrease. This nonlinearity is prevented, however, by compensating for the output transistor's junction capacitance. In one embodiment, compensation circuitry includes a compensation capacitor coupled between the ramp output and a pull-up register attached to a power supply voltage. An input stage includes two transistors, each having a power supply node, an input node, and an output node. The transistors are interconnected at their output nodes, coupled to electrical ground via a current source power supply. The power supply node of the first transistor is coupled to the node connecting the pull-up resistor and the compensation capacitor. The power supply node of the second transistor is coupled to a second pull-up register attached to the power supply. The first transistor receives a reset signal input to the ramp, whereas the second transistor receives a trigger signal that is the inverse of the reset signal.

Abstract translation: 斜坡电路重复地产生基本线性的斜坡信号。 否则会导致非线性输出的斜坡开关结电容被补偿，以提高信号线性度并实现更快的重新触发。 斜坡包括输出晶体管，其输出耦合到电流源和电荷存储装置。 当晶体管导通时，输出电荷存储器件充电。 当晶体管关断时，输出电荷存储器件放电，导致斜坡信号变化。 输出晶体管固有地包括结电容，其导致电荷存储装置的放电中的非线性。 这种非线性似乎是相对于较慢的稳态下降速率的斜坡信号的快速下降。 然而，通过补偿输出晶体管的结电容，可以防止这种非线性。 在一个实施例中，补偿电路包括耦合在斜坡输出和连接到电源电压的上拉寄存器之间的补偿电容器。 输入级包括两个晶体管，每个具有电源节点，输入节点和输出节点。 晶体管在其输出节点处互连，通过电流源电源耦合到电接地。 第一晶体管的电源节点耦合到连接上拉电阻和补偿电容的节点。 第二晶体管的电源节点耦合到附接到电源的第二上拉寄存器。 第一晶体管接收输入到斜坡的复位信号，而第二晶体管接收与复位信号相反的触发信号。

公开(公告)号：US4876216A

公开(公告)日：1989-10-24

申请号：US164556

申请日：1988-03-07

Applicant: Eric Tobias ,  Chau-Shiong A. Chen

Inventor： Eric Tobias ,  Chau-Shiong A. Chen

IPC: H01L21/762

CPC classification number: H01L21/76229

Abstract: In a method of semiconductor integrated circuit manufacture, a manufacturing process improvement provides highly planar, oxide-filled trench isolation of circuit device areas. The process improvement includes formation of a device area covered by a relatively thin insulating layer of oxide by a trenching process that forms a trench adjacent the device area. The thin insulating layer of oxide is extended over the side surface transition between the device area and the trench and then an insulating layer of crystalline dielectric material relatively thicker than the thin insulating layer is applied, which builds the trench at least to the level of the device area. A first layer of photoresist is applied over the thick insulating layer. The portion of the first photoresist layer overlying the device area is photolithographically removed, and then a second layer of photoresist is applied over the first layer; the second layer is applied to a thickness resulting in a relatively planar surface of photoresist overlying the trench and device area. All of the layers overlying the device area are removed by a process which operates toward the substrate surface on which the device area is formed. The removal process removes the first and second photoresist layers, the oxide of the relatively thin layer, and the crystalline dielectric material at substantially the same rate until the device area is expoded. When the device area is exposed, the removal process is terminated. The result provides a device area isolated by an oxide-filled trench, with the surface transition from the device area to the trench oxide being relatively planar.

Abstract translation: 在半导体集成电路制造的方法中，制造工艺改进提供电路器件区域的高度平面的，氧化物填充的沟槽隔离。 工艺改进包括通过开沟工艺形成由相对较薄的氧化物绝缘层覆盖的器件区域，所述开沟工艺形成邻近器件区域的沟槽。 氧化物的薄绝缘层在器件区域和沟槽之间的侧表面跃迁上延伸，然后施加比薄绝缘层更厚的晶体介质材料的绝缘层，其将沟槽至少构成至 设备区域。 将第一层光致抗蚀剂施加在厚绝缘层上。 光刻地除去覆盖在器件区域上的第一光致抗蚀剂层的部分，然后在第一层上施加第二层光致抗蚀剂; 将第二层施加到导致覆盖沟槽和器件区域的光致抗蚀剂相对平坦的表面的厚度。 通过对其上形成有器件区域的衬底表面进行操作的工艺来去除覆盖器件区域的所有层。 去除工艺以基本上相同的速率去除第一和第二光致抗蚀剂层，较薄层的氧化物和结晶介电材料，直到器件区域被覆盖。 当设备区域暴露时，移除过程终止。 结果提供了由氧化物填充的沟槽隔离的器件区域，从器件区域到沟槽氧化物的表面跃迁是相对平面的。

公开(公告)号：US4874970A

公开(公告)日：1989-10-17

申请号：US193261

申请日：1988-05-11

Applicant: Bruce H. Coy ,  Raymond C. Yuen

Inventor： Bruce H. Coy ,  Raymond C. Yuen

IPC: H03K19/013 ,  H03K19/018

CPC classification number: H03K19/01812 ,  H03K19/0136

Abstract: The described embodiment of the present invention provides an output drive circuit having an input circuit comprising a differentially coupled pair of transistors. The output of the differentially paired transistors is provided to a pair of output driver transistors connected in a Darlington or a common collector-common emitter configuration which provides an output pull up signal to an output pin of the integrated circuit containing the described output driver. The opposite output of the differentially coupled pair is provided to a circuit which provides a pull down pulse to quickly shut off the transistor pair during the high to low transition of the output driver transistor. The use of the output driver transistor driver minimizes the current required by the differential pair and the fast pull down circuit eliminates the speed disadvantage of using a transistor pair output driver.

Abstract translation: 本发明的所述实施例提供一种具有输入电路的输出驱动电路，该输入电路包括差分耦合的一对晶体管。 差分配对晶体管的输出被提供给以达林顿连接的一对输出驱动晶体管或公共集电极公共发射极配置，其向包含所述输出驱动器的集成电路的输出引脚提供输出上拉信号。 差分耦合对的相对输出被提供给一个电路，该电路在输出驱动晶体管的高到低转变期间提供一个下拉脉冲来快速切断晶体管对。 输出驱动器晶体管驱动器的使用使差分对所需的电流最小化，并且快速下拉电路消除了使用晶体管对输出驱动器的速度缺点。