公开(公告)号：US20240015951A1

公开(公告)日：2024-01-11

申请号：US17861281

申请日：2022-07-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： JHEN-YU TSAI

IPC分类号： H01L27/108

CPC分类号： H01L27/10823 ,  H01L27/10814 ,  H01L27/10876

摘要： A semiconductor device with a passing gate is provided. The semiconductor device includes a substrate having a first trench and a first gate structure in the first trench. The first gate structure includes a first gate electrode having a first doped region.

公开(公告)号：US20240015947A1

公开(公告)日：2024-01-11

申请号：US17861743

申请日：2022-07-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Jhen-Yu TSAI

IPC分类号： H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10823

摘要： The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a trench in a substrate and disposing a lower gate electrode in the trench. The method also includes disposing a first dielectric layer on the lower gate electrode in the trench and partially removing the first dielectric layer to expose a portion of the lower gate electrode

公开(公告)号：US20240014127A1

公开(公告)日：2024-01-11

申请号：US17811067

申请日：2022-07-06

申请人： NANYA TECHNOLOGY CORPORATION

发明人： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC分类号： H01L23/525 ,  H01L27/112

CPC分类号： H01L23/5252 ,  H01L27/11206 ,  H01L23/5256

摘要： A method of manufacturing a semiconductor device is provided. The method includes providing a substrate having an active area and forming a first diffusion area in the active area. The method also includes disposing a nitride layer on the active area and forming an opening in the nitride layer to expose the first diffusion area. The method also includes disposing an oxide layer in the opening to contact the first diffusion area.

公开(公告)号：US20240013844A1

公开(公告)日：2024-01-11

申请号：US17859204

申请日：2022-07-07

申请人： NANYA TECHNOLOGY CORPORATION

发明人： WU-DER YANG

IPC分类号： G11C17/16 ,  H01L27/112 ,  G11C17/18

CPC分类号： G11C17/16 ,  H01L27/11206 ,  G11C17/18

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure extending along a first direction and electrically connected to a first transistor, a second gate structure extending along the first direction and electrically connected to a second transistor, a first active region extending along a second direction different from the first direction and across the first gate structure and the second gate structure, and a first conductive element extending along the second direction and disposed on the first active region. The first conductive element is electrically connected to the first active region. The first conductive element is electrically connected to the first active region, such that a short circuit between the first active region and the third transistor is formed. The first gate structure and the first active region form a first fuse element, and the second gate structure and the first active region form a second fuse element.

公开(公告)号：US20240006321A1

公开(公告)日：2024-01-04

申请号：US18367052

申请日：2023-09-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHIH-TSUNG WU

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/764 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L23/5329 ,  H01L21/76843 ,  H01L21/764 ,  H01L23/5226 ,  H01L21/7682 ,  H01L23/53261 ,  H01L23/5283

摘要： A semiconductor device includes a first lower plug and a second lower plug disposed over a semiconductor substrate. The semiconductor device also includes a first landing pad disposed over a top surface and upper sidewalls of the first lower plug, and a first upper plug disposed over the first landing pad and electrically connected to the first lower plug. A width of the first lower plug is greater than a width of the first upper plug. The semiconductor device further includes a dielectric layer disposed over the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad and the first upper plug are disposed in the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

公开(公告)号：US20240006232A1

公开(公告)日：2024-01-04

申请号：US18470410

申请日：2023-09-19

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chao-Wen LAY

IPC分类号： H01L21/768 ,  G11C5/06 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L21/76837 ,  G11C5/063 ,  H01L23/5329 ,  H01L23/5283 ,  H01L21/76828 ,  H10B12/482

摘要： A semiconductor device includes a semiconductor structure including a conductive feature therein, a bitline over the semiconductor structure, a spacer on a sidewall of the bitline, wherein the first spacer is made of SiCO, a dielectric layer over a top surface of the bitline; and a contact in contact with the dielectric layer and the spacer and connected to the conductive feature of the semiconductor structure.

公开(公告)号：US20240006185A1

公开(公告)日：2024-01-04

申请号：US17853609

申请日：2022-06-29

申请人： NANYA TECHNOLOGY CORPORATION

发明人： YING-CHENG CHUANG

IPC分类号： H01L21/311 ,  H01L21/66

CPC分类号： H01L21/31116 ,  H01L21/31144 ,  H01L22/12

摘要： A method of manufacturing the same is provided. The method includes providing a substrate. The method also includes forming a target layer over the substrate. The method further includes forming a patterned mask structure over the target layer. In addition, the method includes forming an etching stop layer over the patterned mask structure. The method also includes forming an underlayer over the etching stop layer; and performing an etching process to pattern the target layer.

公开(公告)号：US20230420499A1

公开(公告)日：2023-12-28

申请号：US17849764

申请日：2022-06-27

申请人： NANYA TECHNOLOGY CORPORATION

发明人： YING-CHENG CHUANG

IPC分类号： H01L29/06 ,  H01L29/20

CPC分类号： H01L29/0649 ,  H01L29/2003

摘要： A semiconductor device is provided. The semiconductor device includes a substrate, a first isolation structure, and a second isolation structure. The substrate has a first region and a second region. The first isolation structure is disposed within the first region of the substrate. The first isolation structure includes a first dielectric layer and a first nitridation layer disposed between the substrate and the first dielectric layer. The second isolation structure is disposed within the second region of the substrate.

公开(公告)号：US20230420488A1

公开(公告)日：2023-12-28

申请号：US17849768

申请日：2022-06-27

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H01L49/02

CPC分类号： H01L28/60

摘要： A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first bottom electrode layer, and a second bottom electrode layer surrounding the first bottom electrode layer. The semiconductor device also includes a plurality of insulating portions laterally separating the first bottom electrode layer and the second first bottom electrode layer. The semiconductor device further includes a top electrode disposed over and surrounded by the bottom electrode to structure. The top electrode has a ring shape from a top view. In addition, the semiconductor device includes an insulating layer separating the top electrode from the bottom electrode structure.

公开(公告)号：US20230418259A1

公开(公告)日：2023-12-28

申请号：US17808940

申请日：2022-06-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TZU-CHING TSAI

IPC分类号： G05B19/4099

CPC分类号： G05B19/4099 ,  G05B2219/45031

摘要： An etching method includes executing a first etching recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; collecting the second wafer state of the first wafer to generate a first set of data; and analyzing the first set of data and update the first etching recipe to a second etching recipe when the first set of data is not within a predetermined range. The second etching recipe is generated taking into consideration at least one of an etching rate of the second wafer, a rate of rotation of the second wafer, a tilt angle of the second wafer, an implanting recipe of the first wafer, and a deposition recipe of the first wafer. The second etching recipe is configured to be applied on a second wafer to be processed after the first wafer.