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公开(公告)号:US20200227885A1
公开(公告)日:2020-07-16
申请号:US16743856
申请日:2020-01-15
Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED , STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor: Denise LEE , Neale DUTTON , Nicolas MOENECLAEY , Jerome ANDRIOT-BALLET
Abstract: A laser diode driver circuit includes a first pair of contacts and connectors coupled to an anode of the laser diode. An inductance of each of the first pair of contacts and connectors is the same. A second pair of contacts and connectors are coupled to a cathode of the laser diode. An inductance of each of the second pair of contacts and connectors is the same. The laser diode driver circuit also includes current driving circuitry.
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102.
公开(公告)号:US20200227382A1
公开(公告)日:2020-07-16
申请号:US16835793
申请日:2020-03-31
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: David AUCHERE , Asma HAJJI , Fabien QUERCIA , Jerome LOPEZ
IPC: H01L23/00 , H01L23/552 , H01L23/31
Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
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103.
公开(公告)号:US20200097294A1
公开(公告)日:2020-03-26
申请号:US16573299
申请日:2019-09-17
Inventor: Sebastien METZGER , Silvia BRINI
IPC: G06F9/38 , G06F9/48 , G06F12/084 , G06F13/16
Abstract: A processor interacts with a memory set including a cache memory, a first memory storing at least a first piece of information in a first information group, and a second memory storing at least a second piece of information in a second information group. In response to a first cache miss and following a first request from the processor for the first piece of information, the first piece of information obtained from the first memory is supplied to the processor. After a second request from the processor for the second piece of information, the second piece of information obtained from the second memory is supplied to the processor, even if the first information group is currently being transferred from the first memory for loading into the cache memory.
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公开(公告)号:US10594263B2
公开(公告)日:2020-03-17
申请号:US15983287
申请日:2018-05-18
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Flavia Amorosa , Serge Ramet , Daniel Subiela
Abstract: In an embodiment, a differential amplifier includes: an input stage; an output stage coupled to the input stage, the output stage having first and second output terminals; and a feedback circuit coupled to the output stage, where the feedback circuit is configured to dynamically adjust a bias current of the output stage based on voltages of the first and second output terminals.
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公开(公告)号:US10578672B2
公开(公告)日:2020-03-03
申请号:US14986053
申请日:2015-12-31
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: David Jacquet , Didier Fuin
IPC: G01R31/317 , G01R31/3177 , G01R31/3185
Abstract: A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.
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公开(公告)号:US10528422B2
公开(公告)日:2020-01-07
申请号:US15810731
申请日:2017-11-13
Applicant: STMicroelectronics International N.V. , STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS
Inventor: Om Ranjan , Riccardo Gemelli , Denis Dutey
Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
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公开(公告)号:US20190376676A1
公开(公告)日:2019-12-12
申请号:US16439308
申请日:2019-06-12
Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED , STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor: Joseph HANNAN , Stuart ROBERTSON , Romain COFFY , Jean-Michel RIVIERE
Abstract: The disclosure concerns a housing for a light source mounted on a substrate, the housing comprising: a molded body having an opening permitting the passage of a light beam generated by the light source; one or more surfaces for receiving a diffuser; and first and second conducting pins traversing the molded body, each pin abutting one of said surfaces.
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公开(公告)号:US20190355674A1
公开(公告)日:2019-11-21
申请号:US16411960
申请日:2019-05-14
Inventor: Denis FARISON , Romain COFFY , Jean-Michel RIVIERE
IPC: H01L23/00 , H01L23/528 , H01L21/56 , H01L25/065
Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
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公开(公告)号:US10483181B2
公开(公告)日:2019-11-19
申请号:US16035083
申请日:2018-07-13
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Karine Saxod , Nicolas Mastromauro
Abstract: An integrated circuit chip is mounted to a front face of a support plate. An encapsulation cap in then mounted to the support plate. The encapsulation cap includes a front wall and a peripheral wall having an end edge at least partly facing a peripheral zone of the support plate. The support plate and the encapsulation cap delimit a chamber in which the integrated circuit chip is situated. To mount the encapsulation cap, a bead of glue is inserted between the peripheral zone and the end edge of the peripheral wall of the encapsulation cap. A peripheral outer face of the encapsulation cap includes a recess extending from the end edge which locally uncovers a part of the bead of glue. A local hardening of the glue at the recess is performed as a first attachment step. Further hardening of the remainder of the glue is then performed.
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公开(公告)号:US20190267349A1
公开(公告)日:2019-08-29
申请号:US16282594
申请日:2019-02-22
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Marie-Astrid PIN , Karine SAXOD , Jean-Michel RIVIERE
IPC: H01L23/00 , H01L31/0203 , H01L33/48 , H01L21/78
Abstract: Individual electronic units are formed by cutting a collective assembly. A collective support plate is provided which includes electronic chips. A collective cover plate is provided which includes ribs defining recesses. The collective assembly is formed by mounting the collective cover plate to the collective support plate in a manner where the electronic chips are located in the recesses and the ribs are located between electronic chips. A bead of glue is interposed between ends of the ribs and the surface of the collective support plate. After the glue is hardened, a cutting operation is performed on the collective assembly by cutting through the ribs and the collective support plate to produce the individual electronic units.
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