公开(公告)号：US20140313066A1

公开(公告)日：2014-10-23

申请号：US14214341

申请日：2014-03-14

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Dennis A. Dempsey

IPC: H03M1/68

CPC classification number: H03M1/68 ,  H03M1/00 ,  H03M1/06 ,  H03M1/66 ,  H03M1/682 ,  H03M1/765

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. In one configuration, the DAC comprises a first and second switching network, the second switching network providing multiple switched paths which compensate for impedance effects of the second string and provides multiple state changes at the output node of the DAC.

Abstract translation: 描述多串DAC并且包括至少两个DAC级。 每个DAC级包括一串阻抗元件和一个交换网络。 在一种配置中，DAC包括第一和第二交换网络，第二交换网络提供多个交换路径，其补偿第二串的阻抗效应，并在DAC的输出节点处提供多个状态改变。

公开(公告)号：US08860500B2

公开(公告)日：2014-10-14

申请号：US13945978

申请日：2013-07-19

Applicant: Analog Devices Technology

Inventor： Linus Sheng ,  Christopher W. Mangelsdorf

IPC: G05F3/02

CPC classification number: G05F3/02 ,  H02M3/07 ,  H02M2003/075

Abstract: An apparatus for transferring charge has a first charge pump path with a plurality of stages having first capacitors, and a second charge pump path, also with a plurality of stage having second capacitors, in parallel with the first charge pump path. The first and second charge pump paths are coupled to share a common output node. The apparatus also has a timing circuit coupled with the first and second charge pump paths. Among other things, the timing circuit is configured to cause at least one of the first capacitors to periodically charge at least one of the second capacitors.

Abstract translation: 一种用于传送电荷的装置具有第一电荷泵路径，其具有多个阶段，该第一电荷泵路径具有第一电容器，第二电荷泵路径也具有与第一电荷泵路径并联的具有第二电容器的多个级。 第一和第二电荷泵路径被耦合以共享公共输出节点。 该装置还具有与第一和第二电荷泵路径耦合的定时电路。 其中，定时电路被配置为使得第一电容器中的至少一个周期性地对第二电容器中的至少一个充电。

公开(公告)号：US20140285369A1

公开(公告)日：2014-09-25

申请号：US14214405

申请日：2014-03-14

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Dennis A. Dempsey

IPC: H03M1/66

CPC classification number: H03M1/68 ,  H03M1/00 ,  H03M1/06 ,  H03M1/66 ,  H03M1/682 ,  H03M1/765

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. A control loop is provided to control the Ron of the switching network and provide code dependent control of switches in a DAC switching network.

Abstract translation: 描述多串DAC并且包括至少两个DAC级。 每个DAC级包括一串阻抗元件和一个交换网络。 提供控制回路来控制交换网络的Ron，并提供DAC交换网络中交换机的代码相关控制。

公开(公告)号：US20140269970A1

公开(公告)日：2014-09-18

申请号：US13796236

申请日：2013-03-12

Applicant: Patrick PRATT ,  Peadar Antony FORBES

Inventor： Patrick PRATT ,  Peadar Antony FORBES

IPC: H04B1/04 ,  H04L5/14

CPC classification number: H04B1/0475 ,  H04B1/10 ,  H04B1/123 ,  H04B1/525 ,  H04L5/14 ,  H04L5/1423 ,  H04L5/1461

Abstract: An all digital model of nonlinear transmitter signal distortion in signals received at a receiver of a transmitter-receiver may be used to estimate distortion. The estimated distortion may then be cancelled from the received signals to improve signal quality of the received signal. The digital nonlinear model may be part of an estimator circuit that estimates nonlinear distortion terms by applying a formula or transformation to a digitized version of the signals transmitter at a transmitter of the transmitter-receiver. A mixer may be used to shift a frequency of the estimated nonlinear terms away from a transmitter frequency so that the nonlinear terms can later be subtracted from the incoming signal received at the receiver at a receiver frequency. Circuits and methods are provided.

Abstract translation: 可以使用在发射机 - 接收机的接收机处接收的信号中的非线性发射机信号失真的全数字模型来估计失真。 然后可以从接收的信号中消除估计的失真，以改善接收信号的信号质量。 数字非线性模型可以是通过在发射机 - 接收机的发射机处对信号发射机的数字化版本应用公式或变换来估计非线性失真项的估计器电路的一部分。 可以使用混频器将估计的非线性项的频率偏离发射机频率，使得可以在接收机频率处从接收机接收的输入信号中减去非线性项。 提供电路和方法。

公开(公告)号：US20140269852A1

公开(公告)日：2014-09-18

申请号：US13801130

申请日：2013-03-13

Applicant: Patrick PRATT ,  Peadar Antony FORBES ,  David J. McLAURIN ,  Martin McCORMICK

Inventor： Patrick PRATT ,  Peadar Antony FORBES ,  David J. McLAURIN ,  Martin McCORMICK

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  H04B1/525

Abstract: Transmitter noise cancellation may be applied on a channel by channel basis to active channels of an incoming radio frequency signal received at a receiver. A noise cancellation filter may be provided for each active channel in a predetermined signal band. Applying noise cancellation on a per active channel basis instead of to the entire receive band may substantially reduce the filtering requirement and number of filter coefficients or taps to save power and reduce manufacturing costs. Channelized transmitter noise cancellers, multi transmitter-receiver cross coupling cancellers, and hybrid full signal band and channelized transmitter noise cancellers are also provided.

Abstract translation: 发射机噪声消除可以在逐个信道的基础上应用于在接收机处接收的输入射频信号的有效信道。 可以在预定信号频带中为每个有源信道提供噪声消除滤波器。 在每个活动通道基础上而不是整个接收频带上应用噪声消除可以大大降低滤波器要求和滤波器系数或抽头的数量以节省功率并降低制造成本。 还提供信道化发射机噪声消除器，多发射机 - 接收机交叉耦合消除器，以及混合全信号频带和信道化发射机噪声消除器。

公开(公告)号：US20140266825A1

公开(公告)日：2014-09-18

申请号：US13920083

申请日：2013-06-18

Applicant: Analog Devices Technology

Inventor： Zhao Li ,  Shipra Bhal ,  Kevin Glenn Gard ,  David Alldred ,  Christopher Mayer ,  Trevor Clifford Caldwell ,  David J. McLaurin ,  Victor Kozlov

IPC: H03M1/10

CPC classification number: H03M3/384 ,  H03M1/00 ,  H03M1/1009 ,  H03M1/12 ,  H03M3/458

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract translation: 用于模数转换器（ADC）的校准系统，内部ADC接收模拟输入并将模拟输入转换为数字多位数据。 该校准系统还包括一个参考混洗电路，它洗牌内部ADC的比较器参考值。 此外，校准系统包括校准电路，校准内部ADC的比较器。 校准系统包括基于数字多位数据测量幅度的数字块。 此外，校准系统包括基于数字块的输出来控制校准电路的校准逻辑。

公开(公告)号：US20140266122A1

公开(公告)日：2014-09-18

申请号：US13827666

申请日：2013-03-14

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Zhijie Zhu ,  Junxiao Chen ,  Bin Shao

IPC: H02M3/156

CPC classification number: H02M3/156 ,  H02M2003/1566

Abstract: Apparatus and methods for generating a drive signal of a switching signal are disclosed. A first circuit receives an oscillating reference signal, a first compensation signal, a second compensation signal, and a third compensation signal. The first compensation signal is indicative of an error between an output voltage of a power converter and a reference voltage. The second compensation signal is indicative of the error relative to a threshold. The third compensation signal is indicative of an output current of the power converter. The first circuit generates a comparison signal having a waveform including pulses having durations based at least partly on a combination of the periodic reference signal, the first compensation signal, the second compensation signal, and the third compensation signal. A second circuit receives a clock signal and the comparison signal and generates a drive signal for activation and deactivation of a driver transistor.

Abstract translation: 公开了用于产生开关信号的驱动信号的装置和方法。 第一电路接收振荡参考信号，第一补偿信号，第二补偿信号和第三补偿信号。 第一补偿信号表示功率转换器的输出电压与参考电压之间的误差。 第二补偿信号指示相对于阈值的误差。 第三补偿信号表示功率转换器的输出电流。 第一电路产生具有波形的比较信号，该波形包括至少部分地基于周期性参考信号，第一补偿信号，第二补偿信号和第三补偿信号的组合的具有持续时间的脉冲。 第二电路接收时钟信号和比较信号并产生用于驱动晶体管的激活和去激活的驱动信号。

公开(公告)号：US20140253176A1

公开(公告)日：2014-09-11

申请号：US13792835

申请日：2013-03-11

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Finbarr O'Leary ,  Michael Edward Bradley ,  Naiqian Ren ,  George R. Spalding ,  Nigel David Brooke

IPC: H03K5/22

CPC classification number: H03K5/22

Abstract: A ping pong comparator voltage monitoring circuit which includes first and second comparators having inputs connected to a voltage Vin to be monitored, and second inputs connected to first and second nodes, respectively. A multiplexer alternately couples the first and second comparator outputs to an output in response to a periodic control signal. A ground-referenced voltage Vref1 is provided at a third node and a voltage Vref2 referenced to Vref1 is at a fourth node. A hysteresis hyst1 is switchably connected between the third and first nodes, and a hysteresis hyst2 is switchably connected between the fourth and second nodes. Hyst1 and hyst2 are switched in when the mux output toggles due to a rising Vin, and are switched out when the mux output toggles due to a falling Vin.

Abstract translation: 乒乓比较器电压监视电路，其包括具有连接到要监视的电压Vin的输入的第一和第二比较器，以及分别连接到第一和第二节点的第二输入。 复用器响应于周期性控制信号将第一和第二比较器输出交替耦合到输出。 在第三节点处提供地参考电压Vref1，并且参考Vref1的电压Vref2在第四节点处。 迟滞hyst1可切换地连接在第三节点和第一节点之间，并且滞后hyst2可切换地连接在第四节点和第二节点之间。 当Mux输出由于Vin上升而切换时，Hyst1和hyst2被切换，并且当多路复用器输出由于Vin下降而切换时，Hyst1和hyst2被切换。

公开(公告)号：US20140253083A1

公开(公告)日：2014-09-11

申请号：US13791240

申请日：2013-03-08

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Bin Shao

IPC: G05F1/618

CPC classification number: H02M3/157 ,  H02M1/32 ,  H02M2001/0009 ,  H02M2001/0035

Abstract: In one aspect, this disclosure relates to a method of controlling current output from a switching regulator to a load via an inductor. Inductor current information can be sampled at a peak level, such as just before a transistor configured to cause current to flow through the inductor is turned off. The sampled inductor current can be compared with a reference current, and a current limit threshold can be adjusted based on the comparison. The output current of the switching regulator can be controlled based on a comparison of the current limit threshold with an indicator of current flowing through the inductor. This method can accurately and efficiently limit current in a switching regulator.

Abstract translation: 一方面，本公开涉及一种通过电感器控制从开关调节器到负载的电流输出的方法。 电感电流信息可以在峰值电平进行采样，例如在配置为使电流流过电感器的晶体管关闭之前。 可以将采样的电感电流与参考电流进行比较，并且可以基于比较来调整限流阈值。 可以基于电流限制阈值与流过电感器的电流指标的比较来控制开关稳压器的输出电流。 该方法可以准确有效地限制开关稳压器中的电流。

公开(公告)号：US08779958B1

公开(公告)日：2014-07-15

申请号：US13747241

申请日：2013-01-22

Applicant: Roberto S. Maurino ,  Sanjay Rajasekhar ,  Abhilasha Kawle

Inventor： Roberto S. Maurino ,  Sanjay Rajasekhar ,  Abhilasha Kawle

IPC: H03M1/66 ,  H03M3/00 ,  H03M1/74

CPC classification number: H03M3/35 ,  H03M3/376 ,  H03M3/47

Abstract: A continuous time input stage including a first digital-to-analog converter (DAC) including a first DAC code input, a second DAC including a second DAC code input, a first set of switches coupled to the output of the first DAC, a second set of switches coupled to the output of the second DAC, and an amplifier configured to receive the output of either the first DAC or the second DAC.

Abstract translation: 连续时间输入级包括包括第一DAC代码输入的第一数模转换器（DAC），包括第二DAC代码输入的第二DAC，耦合到第一DAC的输出的第一组开关，第二DAC 耦合到第二DAC的输出的开关组以及被配置为接收第一DAC或第二DAC的输出的放大器。