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公开(公告)号：US20160350240A1
公开(公告)日：2016-12-01
申请号：US14726190
申请日：2015-05-29
Applicant: ANALOG DEVICES GLOBAL
Inventor： Richard F. Grafton , Shivakumar Patil , James Potts , Lewis F. Lahr
CPC classification number: G06F13/1668 , G06F13/4282
Abstract: A serial peripheral interface (SPI) host port is disclosed that enables a host external to a processor to access the processor's memory-mapped resources using SPI memory command protocol. An exemplary processor can include a system interconnect connected to memory-mapped resources and a SPI host port connected to the system interconnect. The SPI host port is configured to use SPI memory command protocol to access memory-mapped resources of the processor for the host external to the processor.
Abstract translation: 公开了一种串行外设接口（SPI）主机端口，使得处理器外部的主机能够使用SPI存储器命令协议访问处理器的存储器映射资源。 示例性处理器可以包括连接到存储器映射资源的系统互连和连接到系统互连的SPI主机端口。 SPI主机端口配置为使用SPI存储器命令协议来访问处理器外部处理器的内存映射资源。
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公开(公告)号：US20160341769A1
公开(公告)日：2016-11-24
申请号：US15229815
申请日：2016-08-05
Applicant: Analog..Devices..Global
Inventor： Seyed Amir Ali Danesh , Jonathan Ephraim David Hurwitz
IPC: G01R19/00
CPC classification number: G01R19/00 , G01R19/16547 , G01R19/2506 , G01R21/06 , G01R23/02 , G01R31/025 , G01R35/005 , H02H1/0015 , H02H3/006 , H02H3/32
Abstract: The present invention relates to current measurement apparatus. The current measurement apparatus comprises first and second measurement devices with each of the first and second measurement devices being operative to measure current in a respective one of a live conductor and a neutral conductor substantially simultaneously. The current measurement apparatus is operative to make plural different determinations in dependence on the substantially simultaneous current measurements.
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公开(公告)号：US20160334818A1
公开(公告)日：2016-11-17
申请号：US14713312
申请日：2015-05-15
Applicant: Analog Devices Global
Inventor： Amit Kumar Singh , Nitish Kuttan , Sriram Ganesan
IPC: G05F1/56
CPC classification number: G05F1/56
Abstract: A regulator circuit can include a cascaded topology, comprising a first integrated low-dropout (LDO) regulator circuit having a supply node, the first integrated LDO regulator circuit configured to provide a first loop bandwidth and configured to provide a regulated first output voltage to an intermediate node using energy provided by the supply node, and a second integrated LDO regulator circuit having an input coupled to the intermediate node, the second LDO regulator circuit configured to provide a second loop bandwidth and configured to provide a regulated second output voltage to an output node, where the second loop bandwidth is narrower than the first loop bandwidth. The regulator circuit need not require an external capacitor. The regulator circuit can be used to provide one or more of enhanced power supply rejection and noise performance.
Abstract translation: 调节器电路可以包括级联拓扑，其包括具有供电节点的第一集成低压差（LDO）调节器电路，所述第一集成LDO调节器电路被配置为提供第一环路带宽并且被配置为将调节的第一输出电压提供给 中间节点使用由所述供应节点提供的能量，以及第二集成LDO调节器电路，其具有耦合到所述中间节点的输入，所述第二LDO调节器电路被配置为提供第二环路带宽并且被配置为向输出端提供调节的第二输出电压 节点，其中第二环路带宽比第一环路带宽窄。 调节器电路不需要外部电容器。 调节器电路可用于提供增强的电源抑制和噪声性能中的一个或多个。
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公开(公告)号：US09475694B2
公开(公告)日：2016-10-25
申请号：US13741198
申请日：2013-01-14
Applicant: ANALOG DEVICES GLOBAL
Inventor： Arturo Martizon, Jr. , Thomas M. Goida
IPC: G01C19/00 , B81C3/00 , B81B7/00 , H01L23/495
CPC classification number: B81C3/008 , B81B7/0074 , H01L23/49555 , H01L2224/48091 , H01L2224/48247 , H01L2924/1461 , H01L2924/181 , H01L2924/1815 , Y10T29/49117 , Y10T156/10 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: Vertical mount package assemblies and methods for making the same are disclosed. A method for manufacturing a vertical mount package assembly includes providing a base substrate having electrical connections for affixing to external circuitry, and providing a package having a mounting region configured to receive a device therein. Flexible electrical leads are formed between the base substrate and the package. The flexible leads can include a plurality of aligned grooves to guide bending. After forming the flexible electrical leads, the package is rotated relative to the base substrate. The aligned grooves can constrain the relative positions of the substrates during rotation, and the beveled edges of the base substrate and package can maintain a desired angular relationship (e.g., perpendicular) between the base substrate and the package after rotation.
Abstract translation: 公开了垂直安装的封装组件及其制造方法。 一种用于制造垂直安装封装组件的方法，包括提供具有用于固定到外部电路的电连接的基底基板，以及提供具有被配置为在其中接收设备的安装区域的封装。 柔性电引线形成在基底基板和封装之间。 柔性引线可以包括多个对准的沟槽以引导弯曲。 在形成柔性电引线之后，封装相对于基底基板旋转。 对准的沟槽可以在旋转期间约束衬底的相对位置，并且基底衬底和封装的斜边缘可以在旋转之后保持基底衬底和封装之间的期望的角度关系（例如，垂直）。
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115.发明申请DC LINEAR VOLTAGE REGULATOR COMPRISING A SWITCHABLE CIRCUIT FOR LEAKAGE CURRENT SUPPRESSION 有权包含用于泄漏电流抑制的可切换电路的直流线性稳压器公开(公告)号：US20160291618A1
公开(公告)日：2016-10-06
申请号：US14673137
申请日：2015-03-30
Applicant: Analog Devices Global
Inventor： Ulrik Sørensen Wismar , Khiem Quang Nguyen
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: The present invention relates in one aspect to a DC linear voltage regulator circuit for generating a regulated DC output voltage based on a DC input voltage. The DC linear voltage regulator circuit comprises a DMOS pass transistor comprising drain, gate, source and bulk terminals wherein the drain terminal is connected to a regulator output which is configured to supply the regulated DC output voltage and the source terminal is connected to a regulator input for receipt of the DC input voltage. The DC linear voltage regulator circuit comprises a switchable leakage prevention circuit, connected to the bulk terminal of the DMOS pass transistor, and configured to automatically detect and interrupt a flow of leakage current from the regulator output to the bulk terminal.
Abstract translation: 本发明在一个方面涉及一种用于基于直流输入电压产生稳定的直流输出电压的直流线性稳压器电路。 DC线性稳压器电路包括DMOS传输晶体管，其包括漏极，栅极，源极和体积端子，其中漏极端子连接到调节器输出，该稳压器输出被配置为提供稳压的DC输出电压，并且源极端子连接到调节器输入 用于接收直流输入电压。 直流线性稳压器电路包括可切换的防漏电路，连接到DMOS传输晶体管的批量端子，并被配置为自动检测和中断从稳压器输出到散装端子的漏电流。
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Patent Agency Ranking
公开(公告)号：US20160277046A1
公开(公告)日：2016-09-22
申请号：US14874883
申请日：2015-10-05
Applicant: ANALOG DEVICES GLOBAL
Inventor： Patrick Joseph Pratt , Peadar Antony Forbes
CPC classification number: H04B1/0475 , H04B1/1018 , H04B1/525
Abstract: A method of reducing the noise from a transmitter at an associated receiver is disclosed. Noise contributions in active channels are identified and used to update a shared noise cancellation filter. Excluding signals from inactive channels speeds up the filter convergence to a near optimal solution. Sharing a filter across multiple channels reduces component count and power consumption.
Abstract translation: 公开了一种在相关联的接收机处降低来自发射机的噪声的方法。 识别有源信道中的噪声贡献，并用于更新共享噪声消除滤波器。 从不活动通道中排除信号可将滤波器收敛加速到接近最优解。 跨多个通道共享过滤器可减少组件数量和功耗。
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公开(公告)号：US20160245893A1
公开(公告)日：2016-08-25
申请号：US15048712
申请日：2016-02-19
Applicant: Analog Devices Global
Inventor： Gavin Patrick Cosgrave , Dermot G. O'Keeffe
CPC classification number: G01R33/096 , G01D5/24485 , G01R31/2829 , G01R35/00
Abstract: Sensor error detection with an additional sensing channel is disclosed herein. First, second, third sensing elements can be disposed at angles relative to one another. In some embodiments, the first, second, and third sensing elements can be magnetic sensing elements, such as anisotropic magnetoresistance (AMR) sensing elements. Sensor data from first, second, and third sensing channels, respectively having the first, second, and third sensing elements, can be obtained. Expected third sensing channel data can be determined and compared to the obtained third sensing channel data to indicate error.
Abstract translation: 本文公开了具有附加感测通道的传感器误差检测。 首先，第二感测元件可相对于彼此成角度设置。 在一些实施例中，第一，第二和第三感测元件可以是诸如各向异性磁阻（AMR）感测元件的磁感测元件。 可以获得分别具有第一，第二和第三感测元件的来自第一，第二和第三感测通道的传感器数据。 可以确定预期的第三感测通道数据并将其与获得的第三感测通道数据进行比较以指示误差。
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118.发明授权Apparatus and methods for a cascode amplifier topology for millimeter-wave power application 有权用于毫米波功率应用的共源共栅放大器拓扑的装置和方法公开(公告)号：US09413309B1
公开(公告)日：2016-08-09
申请号：US14668832
申请日：2015-03-25
Applicant: Analog Devices Global
Inventor： Dixian Zhao , Patrick Reynaert , Michael F. Keaveney
CPC classification number: H03F3/193 , H03F1/0233 , H03F3/45188 , H03F2200/451 , H03F2203/45024 , H03F2203/45481
Abstract: Provided herein are apparatus and methods for a cascode amplifier topology for millimeter-wave power application. The cascode amplifier can use a neutralized common source stage cascoded with a bootstrapped common gate stage to provide an amplifier topology having enhanced performance, gain, stability and reliability. Additionally, a bootstrap capacitor of the common gate stage can be patterned between the source fingers and the drain fingers of a cascode transistor so as to improve device performance. Operating as an RF power amplifier, a single-stage cascode amplifier using the neutralized common source stage with the bootstrapped common gate stage can provide greater than 15 dB of power gain to signals of the E band.
Abstract translation: 本文提供了用于毫米波功率应用的共源共栅放大器拓扑的装置和方法。 共源共栅放大器可以使用与自举公共栅极级级联的中和的共源电源级，以提供具有增强的性能，增益，稳定性和可靠性的放大器拓扑。 此外，可以在共源栅极晶体管的源极指和漏极指之间图案化公共栅极级的自举电容器，以便提高器件性能。 作为RF功率放大器，使用具有自举公共栅极级的中和的共源极级的单级共源共栅放大器可以向E波段的信号提供大于15dB的功率增益。
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公开(公告)号：US09411003B2
公开(公告)日：2016-08-09
申请号：US13684213
申请日：2012-11-22
Applicant: Analog Devices Global
Inventor： Seyed Amir Ali Danesh , Jonathan Ephraim David Hurwitz
CPC classification number: G01R19/00 , G01R19/16547 , G01R19/2506 , G01R21/06 , G01R23/02 , G01R31/025 , G01R35/005 , H02H1/0015 , H02H3/006 , H02H3/32
Abstract: The present invention relates to current measurement apparatus. The current measurement apparatus comprises first and second measurement devices with each of the first and second measurement devices being operative to measure current in a respective one of a live conductor and a neutral conductor substantially simultaneously. The current measurement apparatus is operative to make plural different determinations in dependence on the substantially simultaneous current measurements.
Abstract translation: 本发明涉及电流测量装置。 电流测量装置包括第一和第二测量装置，其中第一和第二测量装置中的每一个基本上同时测量活体导体和中性导体的相应一个中的电流。 电流测量装置可操作以根据基本上同时的电流测量值进行多个不同的确定。
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公开(公告)号：US09377327B2
公开(公告)日：2016-06-28
申请号：US13931148
申请日：2013-06-28
Applicant: ANALOG DEVICES GLOBAL
Inventor： Jan Kubik
CPC classification number: G01D5/16 , G01R33/0005 , G01R33/0094 , G01R33/02 , G01R33/09
Abstract: A magnetic direction sensor, comprising a first array of magneto-resistive elements, said array having a first array primary direction and wherein some but not all of the magneto-resistive elements are wholly or partially provided at a first angle to the primary direction, and the remaining elements are also inclined with respect to the primary direction.
Abstract translation: 一种磁方向传感器，包括第一磁阻元件阵列，所述阵列具有第一阵列主方向，并且其中一些但不是全部的磁阻元件全部或部分地设置成与主方向成第一角度，并且 剩余的元件也相对于主要方向倾斜。
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