公开(公告)号：US11972142B2

公开(公告)日：2024-04-30

申请号：US17136510

申请日：2020-12-29

Applicant: Arm Limited

Inventor： Tessil Thomas

IPC: G06F3/06 ,  G06F12/0804

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0804 ,  G06F2212/1032

Abstract: Circuitry comprises packet reception circuitry to receive a data communication packet with a storage classification from sending circuitry, the data communication packet including at least payload data and a target address for storage of the payload data; and storage control circuitry to control writing of the payload data of a given data communication packet by one or more storage devices selected from a set of two or more candidate storage devices each addressable by the target address, the storage control circuitry being responsive to the storage classification received with the given data communication packet and to respective persistence properties associated with the set of two or more candidate storage devices.

公开(公告)号：US11971831B1

公开(公告)日：2024-04-30

申请号：US18077289

申请日：2022-12-08

Applicant: Arm Limited

Inventor： Julian Katenbrink

IPC: G06F13/16

CPC classification number: G06F13/1673 ,  G06F13/1689

Abstract: An apparatus has first-in, first-out buffer circuitry to transfer data from a source domain to a sink domain across a clock domain boundary. The FIFO buffer circuitry has data transfer circuitry; source domain and sink domain data transfer control circuitry to maintain state vectors indicative of a state of the FIFO buffer circuitry in the respective domain; and synchronisation circuitry in each of the source domain and the sink domain to stabilise a signal received from the other of the source domain and the sink domain and to store the received state vector. The synchronisation circuitry is clock-gated by an enable signal and the synchronisation circuitry is responsive to a change in the state of the FIFO buffer circuitry in the respective domain to advance the respective state vector by controlling the enable signal to enable output of elements of the received state vector.

公开(公告)号：US11966785B2

公开(公告)日：2024-04-23

申请号：US16943117

申请日：2020-07-30

Applicant: Arm Limited

Inventor： Dam Sunwoo ,  Supreet Jeloka ,  Saurabh Pijuskumar Sinha ,  Jaekyu Lee ,  Jose Alberto Joao ,  Krishnendra Nathella

IPC: G06F9/46 ,  G06F9/50 ,  G06N5/04 ,  G06N20/00

CPC classification number: G06F9/5044 ,  G06F9/5038 ,  G06F9/505 ,  G06N5/04 ,  G06N20/00

Abstract: A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.

公开(公告)号：US11947962B2

公开(公告)日：2024-04-02

申请号：US16468098

申请日：2017-11-10

Applicant: ARM LIMITED

Inventor： Jacob Eapen ,  Grigorios Magklis ,  Mbou Eyole

IPC: G06F9/315 ,  G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30109

Abstract: In response to a replicate partition instruction specifying partition information defining positions of a plurality of variable size partitions within a result vector, an instruction decoder (20) controls the processing circuitry (80) to generate a result vector in which each partition having more than one data element comprises data values or element indices of a sequence of data elements of a source vector starting or ending at a selected data element position. This instruction can be useful for accelerating processing of data structures smaller than the vector length.

公开(公告)号：US11947460B2

公开(公告)日：2024-04-02

申请号：US17729233

申请日：2022-04-26

Applicant: Arm Limited

Inventor： Vladimir Vasekin ,  David Michael Bull ,  Vincent Rezard ,  Anton Antonov

IPC: G06F12/08 ,  G06F9/38 ,  G06F12/0842 ,  G06F12/0891

CPC classification number: G06F12/0842 ,  G06F9/3816 ,  G06F12/0891 ,  G06F2212/1021

Abstract: Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.

公开(公告)号：US11935580B2

公开(公告)日：2024-03-19

申请号：US17530095

申请日：2021-11-18

Applicant: Arm Limited

Inventor： Edward Martin McCombs, Jr. ,  Hsin-Yu Chen

IPC: G11C7/12 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094

Abstract: One implementation described herein is related to a device having memory with sense amplifiers and precharge blocks arranged in an array with a first side and a second side. The first side has first sense amplifiers and first precharge blocks coupled together with first bitlines, and the second side has second sense amplifiers and second precharge blocks coupled together with second bitlines. The device has a first delay block coupled to the first precharge blocks in the first side of the array, and the first delay block delays precharge of the first bitlines with a first precharge burst in a multi-burst precharge event. The device has a second delay block coupled to the second precharge blocks in the second side of the array, and the second delay block delays precharge of the second bitlines with a second precharge burst in the multi-burst precharge event.

公开(公告)号：US11934272B2

公开(公告)日：2024-03-19

申请号：US17742875

申请日：2022-05-12

Applicant: Arm Limited

Inventor： Reiley Jeyapaul ,  Roxana Rusitoru ,  Jonathan Curtis Beard ,  Kar-Lik Kasim Wong

IPC: G06F11/14

CPC classification number: G06F11/1407

Abstract: An apparatus comprises at least one processor to execute software processes, a memory system to store data for access by the at least one processor, and checkpointing circuitry to trigger saving, to the memory system, of checkpoints of context state associated with at least one software process executed by the at least one processor. The saving of checkpoints is a background process performed by the checkpointing circuitry in the background of execution of the software processes by the at least one processor.

公开(公告)号：US11929129B2

公开(公告)日：2024-03-12

申请号：US17584711

申请日：2022-01-26

Applicant: Arm Limited

Inventor： David Victor Pietromonaco

IPC: H03K5/00 ,  G11C19/28 ,  H03K5/24 ,  H03K19/20

CPC classification number: G11C19/28 ,  H03K5/24 ,  H03K19/20

Abstract: In one implementation, a circuit includes: a comparator; a shift register chain coupled to the comparator; and one or more converters coupled to respective shift registers of the shift register chain, wherein the one or more converters are configured to convert a source of current from a first voltage to a second voltage, and wherein the circuit is configured to selectively transmit an output signal to the one or more converters. In one implementation, the circuit is configured to selectively control modulation for the one or more converters.

公开(公告)号：US20240080193A1

公开(公告)日：2024-03-07

申请号：US18446530

申请日：2023-08-09

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Roberto Avanzi ,  Alexander Klimov

IPC: H04L9/32

CPC classification number: H04L9/32

Abstract: An apparatus comprises counter integrity tree circuitry to maintain a counter integrity tree having a plurality of nodes. The counter integrity tree circuitry is configured to store, in a first node of the counter integrity tree, an encrypted representation of two or more non-repeating counters and in a second, parent, node, an indication of a function value equal to a non-repeating function of the two or more non-repeating counters of the first node. The apparatus comprises integrity checking circuitry configured to check the integrity of the first node using the function value retrieved from the second node.

公开(公告)号：US11923844B2

公开(公告)日：2024-03-05

申请号：US17731846

申请日：2022-04-28

Applicant: Arm Limited

Inventor： Seshagiri Rao Bogi ,  Vinay Chenani ,  Gurupadayya Shidaganti ,  Akshaykumar V Jabi

IPC: H03K19/0185 ,  H03K3/356 ,  H03K17/081 ,  H03K19/003 ,  H03K19/007

CPC classification number: H03K19/007 ,  H03K3/356113 ,  H03K17/08104 ,  H03K19/00315

Abstract: Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.