公开(公告)号：US20250035838A1

公开(公告)日：2025-01-30

申请号：US18463785

申请日：2023-09-08

Applicant: Intel Corporation

Inventor： Boris Vulovic ,  Wenhua Lin

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/125 ,  G02B6/136

Abstract: Disclosed herein are embodiments of a waveguide structure, comprising: a deep rib waveguide on a slab and a plurality of shallow rib waveguides on the slab. The deep rib waveguide has a first etch-depth, the plurality of shallow rib waveguides has a second etch-depth, and the first etch-depth is greater than the second etch-depth.

公开(公告)号：US20250035425A1

公开(公告)日：2025-01-30

申请号：US18463698

申请日：2023-09-08

Applicant: Intel Corporation

Inventor： Wenhua Lin ,  Boris Vulovic

IPC: G01B9/02015

Abstract: Disclosed herein are embodiments of a broadband wavemeter system comprising: a laser source to generate an optical signal having one or more wavelengths; a tap to separate a portion of the optical signal from the laser source; a splitter to split an incoming optical signal from the tap into a plurality of outgoing optical signals; a plurality of wavemeters, each one in the plurality to receive one of the outgoing optical signals from the splitter, in which each wavemeter in the plurality of wavemeters comprises a Mach-Zehnder Interferometer (MZI), and each wavemeter has at least one of free spectral range (FSR) detuning and center wavelength detuning, and a control circuit to collate outputs from individual ones of the plurality of wavemeters to monitor, detect and control the laser source.

公开(公告)号：US12213043B2

公开(公告)日：2025-01-28

申请号：US17130596

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Fabian Oboril ,  Frederik Pasch ,  Cornelius Buerkle ,  Bernd Gassmann ,  Kay-Ulrich Scholl

IPC: H04W4/80 ,  G06Q20/32 ,  H04W4/029

Abstract: Mobility-as-a-Service (MaaS) provides technical solutions for technical problems facing this shift toward public and private vehicles for hire, including providing a platform for users to identify and select public transportation and private vehicles for hire. Users may plan and book transportation services through a MaaS platform, such as a smartphone application. Technical solutions described herein include improved identification and selection of a vehicle based on wireless communication, such as using Near-Field Communication (NFC), Bluetooth, Wi-Fi, and other wireless communication.

公开(公告)号：US12212502B2

公开(公告)日：2025-01-28

申请号：US17084526

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Mark Debbage ,  Robert Southworth ,  Arvind Srinivasan ,  Cheolmin Park ,  Todd Rimmer ,  Brian S. Hausauer

IPC: H04L47/34 ,  H04L1/1607 ,  H04L47/125

Abstract: Examples described herein relate to technologies for reliable packet transmission. In some examples, a network interface includes circuitry to: receive a request to transmit a packet to a destination device, select a path for the packet, provide a path identifier identifying one of multiple paths from the network interface to a destination and Path Sequence Number (PSN) for the packet, wherein the PSN is to identify a packet transmission order over the selected path, include the PSN in the packet, and transmit the packet. In some examples, if the packet is a re-transmit of a previously transmitted packet, the circuitry is to: select a path for the re-transmit packet, and set a PSN of the re-transmit packet that is a current packet transmission number for the selected path for the re-transmit packet. In some examples, a network interface includes circuitry to process a received packet to at least determine a Path Sequence Number (PSN) for the received packet, wherein the PSN is to provide an order of packet transmissions for a path associated with the received packet, process a second received packet to at least determine its PSN, and based on the PSN of the second received packet not being a next sequential value after the PSN of the received packet, cause transmission of a re-transmit request to a sender of the packet and the second packet.

公开(公告)号：US12211117B2

公开(公告)日：2025-01-28

申请号：US17849968

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Dipankar Das ,  Karthikeyan Vaidyanathan ,  Srinivas Sridharan

IPC: G06T1/20 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06T1/60 ,  G06N3/044

Abstract: One embodiment provides for a method of transmitting data between multiple compute nodes of a distributed compute system, the method comprising multi-dimensionally partitioning data of a feature map across multiple nodes for distributed training of a convolutional neural network; performing a parallel convolution operation on the multiple partitions to train weight data of the neural network; and exchanging data between nodes to enable computation of halo regions, the halo regions having dependencies on data processed by a different node.

公开(公告)号：US12210632B2

公开(公告)日：2025-01-28

申请号：US17083149

申请日：2020-10-28

Applicant: Intel Corporation

Inventor： Sundar Vedantham ,  Bin Lin ,  Pravin Pathak ,  Ximing Chen ,  Chris MacNamara

IPC: G06F21/00 ,  G06F16/27 ,  G06F21/60

Abstract: Examples described herein relate to a manner of provide a time of life of data. In some examples, data and control parameters are received from a data source. The data can be encrypted and stored. In addition, at least a portion of the control parameters can be stored into a distributed ledger. In some examples, the portion of the control parameters include an indicator of expiration time of the data. In some examples, a data header for the data is generated, where the data header includes an indication that the data is subject to a limited life span and a data identifier. The data header can be accessed with a request to access the encrypted data. In some examples, a request to determine if the data is valid and accessible is provided to a node of the distributed ledger and an indication of whether the data is valid and accessible is received from a node in the distributed ledger.

公开(公告)号：US12210620B2

公开(公告)日：2025-01-28

申请号：US17203553

申请日：2021-03-16

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F21/55 ,  G06N3/04 ,  G06N3/088

Abstract: Hardware based unsupervised based machine-learning (ML) approach to identify a security threat to the processor (e.g., caused by probing of a power supply rail). An apparatus is provided which includes an on-die power supply droop detector as a feature extractor. The droop detector detects a droop in the power supply caused by a probe physically coupling to the power supply rail. The droop detector in combination with machine-learning logic detects change in power supply rail impedance profile due to a probe coupled to the power supply rail. A deep-neural network (DNN) is provided for feature classification that classifies a security threat from normal operation and from operations caused by aging of devices in the processor. The DNN is trained in a training phase or production phase of the processor. An aging sensor is used to distinguish classification of aged data vs. normal data and data from security attack.

公开(公告)号：US12210446B2

公开(公告)日：2025-01-28

申请号：US18284265

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Lingxiang Xiang ,  Christopher J. Hughes

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/02 ,  G06F12/0811

Abstract: An embodiment of an integrated circuit may comprise circuitry communicatively coupled to two or more sub-non-uniform memory access clusters (SNCs) to allocate a specified memory space in the two or more SNCs in accordance with a SNC memory allocation policy indicated from a request to initialize the specified memory space. An embodiment of an apparatus may comprise decode circuitry to decode a single instruction, the single instruction to include a field for an opcode, and execution circuitry to execute the decoded instruction according to the opcode to provide an indicated SNC memory allocation policy (e.g., a SNC policy hint). Other embodiments are disclosed and claimed.

公开(公告)号：US20250029908A1

公开(公告)日：2025-01-23

申请号：US18904780

申请日：2024-10-02

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Sujit SHARAN ,  Dae-Woo KIM

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/00 ,  H01L23/544 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20250029892A1

公开(公告)日：2025-01-23

申请号：US18223413

申请日：2023-07-18

Applicant: Intel Corporation

Inventor： Conor P. PULS ,  Giorgio MARIOTTINI ,  Brenden ARRUDA ,  Shawna M. LIFF ,  Lei JIANG ,  Samson ODUNUGA ,  Gerardo MONTANO ,  Hannes GREVE ,  Apratim DHAR ,  Aaron M. WHITE

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.