公开(公告)号：US5977864A

公开(公告)日：1999-11-02

申请号：US79641

申请日：1998-05-15

申请人： Michael S. Buonpane ,  Ravi Kumar Kolagotla ,  Jiancheng Mo

发明人： Michael S. Buonpane ,  Ravi Kumar Kolagotla ,  Jiancheng Mo

IPC分类号： G06F7/02 ,  G05B1/00

CPC分类号： G06F7/02

摘要： There is disclosed, a high speed comparator with bit-wise masking takes advantage of early availability of the reference word and mask word to generate conditional select signals, thereby minimizing the time required to generate a comparator output once the input word to be compared is available.

摘要翻译： 已经公开了，具有逐位掩蔽的高速比较器利用参考字和掩码字的早期可用性来产生条件选择信号，由此一旦要比较的输入字可用就最小化产生比较器输出所需的时间 。

公开(公告)号：US5958036A

公开(公告)日：1999-09-28

申请号：US925342

申请日：1997-09-08

申请人： Geoffrey Francis Burns ,  Ravi Kumar Kolagotla ,  Douglas J. Rhodes ,  Marck E. Thierbach

发明人： Geoffrey Francis Burns ,  Ravi Kumar Kolagotla ,  Douglas J. Rhodes ,  Marck E. Thierbach

IPC分类号： G06F9/46

CPC分类号： G06F9/4818 ,  G06F13/24

摘要： Apparatus for arbitrating the selection of an interrupt for servicing from a plurality of interrupts in which a priority level for each of the plurality of interrupts is programmed in a first register and each of the interrupts which is to be evaluated for selection for servicing is set as pending in a second register. Only a pending interrupt having a priority level above a pre-set current interrupt priority level is selected for servicing and where multiple pending interrupts of the same priority level occur, the one with the highest order bit position in the second register is used.

摘要翻译： 用于仲裁从多个中断中选择用于服务的中断的装置，其中，将多个中断中的每一个的优先级编程在第一寄存器中，并且将要评估的每个中断用于服务选择被设置为 等待在第二个注册。 选择具有高于预设当前中断优先级的优先级的待决中断，并且在发生相同优先级的多个未决中断的情况下，使用第二个寄存器中具有最高位位置的中断。

公开(公告)号：US5958011A

公开(公告)日：1999-09-28

申请号：US829579

申请日：1997-03-31

申请人： Ravi Kumar Arimilli ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Jerry Don Lewis

IPC分类号： G06F11/30 ,  G06F13/14

CPC分类号： G06F13/423

摘要： A data processing system and method of communicating data in a data processing system are described. The data processing system includes a communication network to which a plurality of devices are coupled. At least one device among the plurality of devices coupled to the communication network includes mastering circuitry and snooping circuitry. According to the method, a first timing signal having a first frequency and a second timing signal having a second frequency different from the first frequency are generated. Communication transactions on the communication network are initiated utilizing the mastering circuitry, which operates in response to the first timing signal, and are monitored utilizing the snooping circuitry, which operates in response to the second timing signal.

摘要翻译： 描述了在数据处理系统中传送数据的数据处理系统和方法。 数据处理系统包括多个设备耦合到的通信网络。 耦合到通信网络的多个设备中的至少一个设备包括母盘制作电路和窥探电路。 根据该方法，产生具有第一频率的第一定时信号和具有与第一频率不同的第二频率的第二定时信号。 在通信网络上的通信交易是利用主控电路来启动的，该母盘控制电路响应于第一定时信号进行操作，并且利用响应于第二定时信号而工作的监听电路进行监视。

公开(公告)号：US5940611A

公开(公告)日：1999-08-17

申请号：US837519

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/3824

摘要： A method and system for front-end gathering of store instructions within a processor is disclosed. In accordance with the method and system of the present invention, a store queue within a data-processing system includes a front-end queue and a back-end queue. Multiple entries are provided in the back-end queue, and each entry includes an address field, a byte-count field, and a data field. A determination is first made as to whether or not a data field of a first entry of the front-end queue is filled completely. In response to a determination that the data field of the first entry of the front-end queue is not filled completely, another determination is made as to whether or not an address for a store instruction in a subsequent second entry is equal to an address for the store instruction in the first entry plus a byte count in the first entry. In response to a determination that the address for the store instruction in the subsequent second entry is equal to the address for the store instruction in the first entry plus the byte count in the first entry, the store instruction in the subsequent second entry is collapsed into the store instruction in the first entry.

摘要翻译： 公开了一种用于处理器内存储指令前端收集的方法和系统。 根据本发明的方法和系统，数据处理系统内的存储队列包括前端队列和后端队列。 在后端队列中提供多个条目，每个条目包括地址字段，字节计数字段和数据字段。 首先确定前端队列的第一条目的数据字段是否被完全填充。 响应于确定前端队列的第一条目的数据字段未被完全填充，另外确定在后续第二条目中的存储指令的地址是否等于 第一个条目中的存储指令加上第一个条目中的字节数。 响应于确定后续第二条目中的存储指令的地址等于第一条目中的存储指令的地址加上第一条目中的字节计数，则随后的第二条目中的存储指令被折叠成 商店指令在第一个条目。

公开(公告)号：US5931924A

公开(公告)日：1999-08-03

申请号：US839437

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

IPC分类号： G06F15/16 ,  G06F13/364 ,  G06F15/177 ,  G06F13/14

CPC分类号： G06F13/364

摘要： A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is associated with a priority weight that indicates a probability that the associated requester will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requesters. In response to the current priorities of the requesters, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.

摘要翻译： 描述了用于控制对数据处理系统中的共享资源的访问的方法和系统。 根据该方法，通过共享资源的多个请求者生成对资源的访问的多个请求。 每个请求者与优先级权重相关联，该权重指示相关请求者将被分配最高当前优先级的概率。 然后分配每个请求者相对于请求者的先前优先级基本随机确定的当前优先级。 为响应请求者的当前优先级，授予访问资源的请求。 在一个实施例中，与被许可的请求相对应的请求者用信号通知其请求已经被许可，并且与被拒绝的请求相对应的请求者用信号通知其请求未被授予。

公开(公告)号：US5893163A

公开(公告)日：1999-04-06

申请号：US992135

申请日：1997-12-17

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0811

摘要： A method and system for allocating data among cache memories within a symmetric multiprocessor data-processing system are disclosed. The symmetric multiprocessor data-processing system includes a system memory and multiple processing units, wherein each of the processing units has a cache memory. The system memory is divided into a number of segments, wherein the number of segments is equal to the total number of cache memories. Each of these segments is represented by one of the cache memories such that a cache memory is responsible to cache data from its associated segment within the system memory.

摘要翻译： 公开了一种用于在对称多处理器数据处理系统内的高速缓存存储器中分配数据的方法和系统。 对称多处理器数据处理系统包括系统存储器和多个处理单元，其中每个处理单元具有高速缓冲存储器。 系统存储器被分成多个段，其中段的数量等于高速缓冲存储器的总数。 这些段中的每一个由高速缓冲存储器之一表示，使得高速缓冲存储器负责缓存来自系统存储器内的相关段的数据。

公开(公告)号：US5883825A

公开(公告)日：1999-03-16

申请号：US922735

申请日：1997-09-03

申请人： Ravi Kumar Kolagotla

发明人： Ravi Kumar Kolagotla

IPC分类号： G06F7/52

CPC分类号： G06F7/53

摘要： There is disclosed a converter for summing inputs includes first, second, third and fourth adders. Each of the adders is adapted to receive a carry-in and to provide as outputs a carry-out and a sum output. Each adder has an associated partial product generated in proximity thereto. The adders are interconnected such that the associated partial product of the first and second adders provide additional inputs to the first adder. The associated partial products of the third and fourth adder provide additional inputs to the second adder. The sum output of the first and second adders provide additional input to the third adder. A sum input to the converter and the sum output of the third adder provide additional inputs to the fourth adder. The output of the fourth adder is the output of the converter.

摘要翻译： 公开了一种用于求和输入的转换器，包括第一，第二，第三和第四加法器。 每个加法器适于接收进位输入并提供作为输出的进位输出和和输出。 每个加法器具有在其附近生成的相关联的部分乘积。 加法器互连，使得第一和第二加法器的相关联的部分乘积向第一加法器提供额外的输入。 第三和第四加法器的相关联的部分乘积向第二加法器提供附加输入。 第一和第二加法器的和输出向第三加法器提供附加输入。 输入到转换器的和和第三加法器的和输出向第四加法器提供附加输入。 第四加法器的输出是转换器的输出。

公开(公告)号：US5874368A

公开(公告)日：1999-02-23

申请号：US942996

申请日：1997-10-02

申请人： Ravi Kumar Laxman ,  David Allen Roberts ,  Arthur Kenneth Hochberg ,  Herman Gene Hockenhull ,  Felicia Diane Kaminsky

发明人： Ravi Kumar Laxman ,  David Allen Roberts ,  Arthur Kenneth Hochberg ,  Herman Gene Hockenhull ,  Felicia Diane Kaminsky

IPC分类号： C07F7/02 ,  C23C16/34 ,  H01L21/318

CPC分类号： H01L21/02222 ,  C23C16/345 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/3185

摘要： A process for the low pressure chemical vapor deposition of silicon nitride from ammonia and a silane of the formula: (t-C.sub.4 H.sub.9 NH).sub.2 SiH.sub.2 provides improved properties of the resulting film for use in the semiconductor industry.

摘要翻译： 用于氨的氮化硅的低压化学气相沉积和式（t-C 4 H 9 N H）2 SiH 2的硅烷的方法提供了用于半导体工业的所得膜的改进的性能。

公开(公告)号：US5842010A

公开(公告)日：1998-11-24

申请号：US427056

申请日：1995-04-24

申请人： Ravi Kumar Jain ,  John St. Clair Werth, Jr.

发明人： Ravi Kumar Jain ,  John St. Clair Werth, Jr.

IPC分类号： H04J1/00 ,  G06F17/30 ,  H04B7/26 ,  H04H20/28 ,  H04J4/00 ,  H04L5/00

CPC分类号： H04H20/28 ,  H04B7/2615 ,  H04J4/00 ,  Y10S707/99945

摘要： A periodic wireless data transmission has improved access latency obtaining information regarding users' interest in the information and by arranging the information on an transmission in order of descending popularity. In one embodiment, each adjacent pair of topics on the transmission. The topics' positions on the transmission are exchanged if the exchange decreases the average latency for all users. This may be repeated for all of the topics on the transmission. The transmission structure may also be arranged so that the transmission combines a number of transmission channels to obtain greater aggregate capacity. This may be done using, for example, an FDMA transmission structured to be theoretically comparable to a plurality of "striped" disks known as a RAID (redundant array of inexpensive disks).

摘要翻译： 周期性无线数据传输具有改善的访问等待时间，从而获得关于用户对信息的兴趣的信息，并且通过以下降的流行顺序排列关于传输的信息。 在一个实施例中，传输上的每个相邻的主题对。 如果交换减少了所有用户的平均延迟，则交换主题的传输位置。 传输中的所有主题可能会重复这一点。 传输结构也可以被布置成使得传输组合多个传输信道以获得更大的总容量。 这可以使用例如被理论上与被称为RAID（廉价磁盘的冗余阵列）的多个“条带”磁盘相当的FDMA传输来完成。

公开(公告)号：US5796979A

公开(公告)日：1998-08-18

申请号：US730994

申请日：1996-10-16

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jerry Don Lewis

IPC分类号： G06F12/08 ,  G06F13/12

CPC分类号： G06F12/0866 ,  G06F12/0815 ,  G06F12/0835 ,  G06F2212/303

摘要： A data processing system includes a processor, a system memory, one or more input/output channel controllers (IOCC), and a system bus connecting the processor, the memory and the IOCCs together for communicating instructions, address and data between the various elements of a system. The IOCC includes a paged cache storage having a number of lines wherein each line of the page may be, for example, 32 bytes. Each page in the cache also has several attribute bits for that page including the so called WIM and attribute bits. The W bit is for controlling write through operations; the I bit controls cache inhibit; and the M bit controls memory coherency. Since the IOCC is unaware of these page table attribute bits for the cache lines being DMAed to system memory, IOCC must maintain memory consistency and cache coherency without sacrificing performance. For DMA write data to system memory, new cache attributes called global, cachable and demand based write through are created. Individual writes within a cache line are gathered by the IOCC and only written to system memory when the I/O bus master accesses a different cache line or relinquishes the I/O bus.

摘要翻译： 数据处理系统包括处理器，系统存储器，一个或多个输入/输出通道控制器（IOCC）以及将处理器，存储器和IOCC连接在一起的系统总线，用于在各种元件之间传送指令，地址和数据 一个系统。 IOCC包括具有多行的分页缓存存储器，其中页面的每行可以是例如32字节。 缓存中的每个页面还具有该页面的几个属性位，包括所谓的WIM和属性位。 W位用于控制写操作; I位控制缓存抑制; M位控制存储器一致性。 由于IOCC不知道将这些页表属性位用于高速缓存行被DMA映射到系统内存，因此IOCC必须保持内存一致性和高速缓存一致性，而不会牺牲性能。 对于将DMA写入数据到系统内存，创建了称为全局，可高速缓存和基于需求的写入的新缓存属性。 高速缓存行中的单独写入由IOCC收集，只有当I / O总线主机访问不同的高速缓存行或放弃I / O总线时才写入系统存储器。