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公开(公告)号：US20180004270A1
公开(公告)日：2018-01-04
申请号：US15253012
申请日：2016-08-31
Applicant: STMicroelectronics (Alps) SAS
Inventor： Fabien Journet
CPC classification number: G06F1/324 , G06F1/06 , G06F9/3869 , H04B5/0037
Abstract: Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.
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公开(公告)号：US09847798B2
公开(公告)日：2017-12-19
申请号：US14961996
申请日：2015-12-08
Inventor： Julien Saade , Abdelaziz Goulahsen
CPC classification number: H04B1/04 , G06F13/4282 , H04L25/4908
Abstract: The invention relates to a method for serial data transmission, comprising the steps consisting in computing the running disparity (RD) of a bit stream that is being transmitted; when the running disparity reaches a threshold (T), computing a point disparity on a subsequent frame (S) of the stream; if the point disparity has the same sign as the threshold, inverting the states of the bits of the frame in the transmitted bit stream; and inserting into the transmitted bit stream a polarity bit having a state signalling the inversion.
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113.发明申请公开(公告)号：US20170336819A1
公开(公告)日：2017-11-23
申请号：US15364392
申请日：2016-11-30
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
CPC classification number: G05F1/59 , G05F1/56 , G05F1/569 , H01R24/60 , H01R2107/00 , H02J7/022 , H02J7/06 , H02J2007/10 , H03F3/45071 , H03F2203/45521 , H03F2203/45641
Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.
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公开(公告)号：US09813655B2
公开(公告)日：2017-11-07
申请号：US15237103
申请日：2016-08-15
Applicant: STMicroelectronics (Alps) SAS
Inventor： Serge Hembert
CPC classification number: H04N5/44 , G09G5/006 , G09G2340/02 , G09G2370/20 , G09G2370/22 , H04R2420/05
Abstract: A video and/or audio decoder provided with a first terminal for supplying an analog audio and/or video signal, including: a first circuit capable of supplying a digital signal which is an image of said analog signal; a digital-to-analog converter capable of receiving as an input said digital signal; an amplifier coupling a second output terminal of the digital-to-analog converter to the first terminal; and a second circuit capable of comparing a signal representative of the voltage or current level on the first terminal with a reference signal, and of deducing therefrom whether the first terminal is connected or not to an analog input terminal of a video signal display and/or audio signal playing device.
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公开(公告)号：US20170220443A1
公开(公告)日：2017-08-03
申请号：US15253002
申请日：2016-08-31
Applicant: STMicroelectronics (Alps) SAS
Inventor： Mickael Broutin , Benoit Lelievre , Nicolas Anquet
CPC classification number: G06F11/27 , G06F11/0778 , G11C7/24 , G11C29/12 , G11C2029/3602
Abstract: Embodiments of the circuits described include a method wherein at least one command signal is activated. The activation of the at least one command signal causes a request to a testing circuit of a memory array to enter a memory test mode. The requested memory test mode permits at least part of the memory array to be read. In response to activation of the at least one command signal, a test control circuit initiates an overwrite sequence to overwrite the data stored in the memory array. The test control circuit enables the memory test mode once the overwrite sequence has been completed.
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Patent Agency Ranking
公开(公告)号：US09698183B2
公开(公告)日：2017-07-04
申请号：US14744482
申请日：2015-06-19
Inventor： Nicolas Moeneclaey , Julien-Marc Roux , Jerome Bourgoin
IPC: H04N5/374 , H01L27/146 , H04N5/378 , H04N5/367 , H04N17/00 , H04N5/3745
CPC classification number: H01L27/14612 , H01L27/14643 , H04N5/367 , H04N5/374 , H04N5/3742 , H04N5/3745 , H04N5/378 , H04N17/002
Abstract: A CMOS image sensor including: an array of M×N pixels, the pixels of a same column being connected to a same output track, each pixel including a photodiode, a sense node, a transfer transistor, a reset transistor, and a read circuit; and a test circuit including an assembly of N elementary reference cells respectively connected to the N output tracks of the sensor, each cell including a resistor, a sense node, a transfer transistor, a reset transistor, and a read circuit, the N resistors being series-connected between first and second nodes of application of a reference voltage.
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117.发明申请公开(公告)号：US20170179816A1
公开(公告)日：2017-06-22
申请号：US14975138
申请日：2015-12-18
Applicant: STMicroelectronics (Alps) SAS
Inventor： Vratislav MICHAL
IPC: H02M3/04
CPC classification number: H02M3/04 , H02M3/156 , H02M3/1588 , H02M2001/0054 , Y02B70/1466 , Y02B70/1491
Abstract: A method and apparatus for detecting a critical duty cycle that maximizes an output power of a boost converter is provided. In the method and apparatus, boost converter is operated may be operated at or below the critical duty cycle. In the method and apparatus, a first voltage that is a function of an output voltage of a boost converter and voltage drops across a first set of parasitic resistances of the boost converter is detected. A second voltage that is a function voltage drops across a second set of parasitic resistances of the boost converter is also detected. The voltages are compared to determine the critical duty cycle and the boost converter is operated in accordance with a duty cycle that does not exceed the critical duty cycle.
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公开(公告)号：US20170115359A1
公开(公告)日：2017-04-27
申请号：US15076955
申请日：2016-03-22
Applicant: STMicroelectronics (Alps) SAS
Inventor： Bruno LEDUC , Pascal BERNON , Stephane CLIN
CPC classification number: G01R31/40 , G01R3/00 , G01R15/14 , G01R19/165
Abstract: A circuit includes, in series between a first terminal and a second terminal of application of a power supply voltage, and first and second branches. The first branch includes a first transistor and a first current source coupled to the first transistor. The second branch includes a resistive element, a second transistor coupled to the resistive element and forming a current mirror with the first transistor and a second current source coupled to the second transistor. The resistive element conditions a threshold of detection of a variation of the power supply voltage.
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公开(公告)号：US20160233896A1
公开(公告)日：2016-08-11
申请号：US14961996
申请日：2015-12-08
Inventor： Julien SAADE , Abdelaziz GOULAHSEN
CPC classification number: H04B1/04 , G06F13/4282 , H04L25/4908
Abstract: The invention relates to a method for serial data transmission, comprising the steps consisting in computing the running disparity (RD) of a bit stream that is being transmitted; when the running disparity reaches a threshold (T), computing a point disparity on a subsequent frame (S) of the stream; if the point disparity has the same sign as the threshold, inverting the states of the bits of the frame in the transmitted bit stream; and inserting into the transmitted bit stream a polarity bit having a state signalling the inversion.
Abstract translation: 本发明涉及一种用于串行数据传输的方法，包括以下步骤：计算待发送的比特流的运行差异（RD）; 当运行视差达到阈值（T）时，计算流的后续帧（S）上的点差异; 如果点视差具有与阈值相同的符号，则反转发送的比特流中的帧的比特的状态; 并且向所发送的比特流插入具有信号反转的状态的极性比特。
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公开(公告)号：US20160224042A1
公开(公告)日：2016-08-04
申请号：US14868095
申请日：2015-09-28
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
IPC: G05F1/575
CPC classification number: G05F1/575 , H02J1/02 , H02J7/0068 , H02J7/34 , H03K19/0016
Abstract: The present disclosure relates to a voltage regulation circuit including a first transistor connected between an input of voltage to be regulated and an output of a regulated voltage. A first regulation loop controls the first transistor according to a difference between a reference voltage and a first feedback voltage derived from the regulated voltage. A second transistor is connected in series between the first transistor and the output. A second regulation loop controls the second transistor according to a difference between the reference voltage and a second feedback voltage derived from the regulated voltage. The second regulation loop is active in low and high power regulation modes. A switch circuit forces the first transistor into an on state in a low power regulation mode.
Abstract translation: 本公开涉及一种电压调节电路，其包括连接在待调节电压的输入和调节电压的输出之间的第一晶体管。 第一调节环路根据参考电压和从调节电压导出的第一反馈电压之间的差来控制第一晶体管。 第二晶体管串联连接在第一晶体管和输出端之间。 第二调节环路根据参考电压和从调节电压导出的第二反馈电压之间的差来控制第二晶体管。 第二个调节回路在低功率和高功率调节模式下有效。 开关电路迫使第一晶体管处于低功率调节模式的导通状态。
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