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公开(公告)号：US20160293137A1
公开(公告)日：2016-10-06
申请号：US14676544
申请日：2015-04-01
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Peter F. Holland , Guy Cote
IPC: G09G5/02
CPC classification number: G09G5/02 , G09G5/363 , G09G5/391 , G09G2340/0428 , G09G2360/02
Abstract: Systems, apparatuses, and methods for passing source pixel data through a display control unit. A display control unit includes N-bit pixel component processing lanes for processing source pixel data. When the display control unit receives M-bit source pixel components, wherein ‘M’ is greater than ‘N’, the display control unit may assign the M-bit source pixel components to the N-bit processing lanes. Then, the M-bit source pixel components may passthrough the pixel component processing elements of the display control unit without being modified.
Abstract translation: 用于通过显示控制单元传送源像素数据的系统，装置和方法。 显示控制单元包括用于处理源像素数据的N位像素分量处理通道。 当显示控制单元接收M位大于'N'的M位源像素分量时，显示控制单元可以将M位源像素分量分配给N位处理通道。 然后，M位源像素分量可以直接通过显示控制单元的像素分量处理元件而不被修改。
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公开(公告)号：US09262798B2
公开(公告)日：2016-02-16
申请号：US14263424
申请日：2014-04-28
Applicant: Apple Inc.
Inventor： Joseph P. Bratt , Peter F. Holland , Shing Horng Choo , Timothy J. Millet
CPC classification number: G06T1/60 , G09G5/14 , G09G5/363 , G09G2340/10 , G09G2360/12 , G09G2360/127
Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.
Abstract translation: 图形系统可以包括用于处理当前显示帧的一个或多个处理单元，每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组，每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索和处理顶部帧分组，以根据顶部帧分组的内容更新一个或多个参数寄存器。 控制电路可以发出DMA请求，用从系统存储器传送的帧分组填充参数缓冲器，其中帧分组可以由在中央处理单元上执行的应用（或软件）写入。
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公开(公告)号：US09087393B2
公开(公告)日：2015-07-21
申请号：US13788209
申请日：2013-03-07
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Peter F. Holland , Timothy J. Millet
CPC classification number: G06T1/60 , G09G5/006 , G09G2340/0442 , G09G2340/0492 , G09G2360/125 , G09G2370/10
Abstract: In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation.
Abstract translation: 在一个实施例中，系统包括针对与网络显示器进行通信而优化的硬件。 硬件可以包括显示管单元，其被配置为将来自视频序列的一个或多个静态图像和一个或多个帧组合以形成用于由网络显示器显示的帧。 显示管单元可以包括写回单元，其被配置为将复合帧写回到存储器，可以使用视频编码器硬件来选择性地对帧进行编码，并将其分组化以便通过网络传输到网络显示器。 在一个实施例中，显示管单元可以被配置为在帧的生成期间向视频编码器发出中断，以重叠编码和帧生成。
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114.发明授权Multiple quality of service (QoS) thresholds or clock gating thresholds based on memory stress level 有权基于内存应力水平的多种服务质量（QoS）阈值或时钟门控阈值公开(公告)号：US09019291B2
公开(公告)日：2015-04-28
申请号：US13775641
申请日：2013-02-25
Applicant: Apple Inc.
Inventor： Peter F. Holland , Marc A. Schaub
CPC classification number: G06T1/60
Abstract: In an embodiment, a display control unit is configured to transmit read operations to the memory in the system to read image data for processing, and may employ QoS levels with the read operations to ensure that enough data is provided to satisfy the real time display requirements. To determine which QoS level to use for a given read request, the display control unit may be configured to compare an amount of image data in the display control unit (e.g. in various input and/or output buffers in the display control unit) to one or more thresholds. The display control unit may also be configured to dynamically update the thresholds based on a memory stress level in the memory controller.
Abstract translation: 在一个实施例中，显示控制单元被配置为向系统中的存储器发送读取操作以读取用于处理的图像数据，并且可以利用读取操作的QoS级别来确保提供足够的数据以满足实时显示要求 。 为了确定对于给定的读取请求使用哪个QoS级别，显示控制单元可以被配置为将显示控制单元中的图像数据量（例如，在显示控制单元中的各种输入和/或输出缓冲器中）与一个 或更多阈值。 显示控制单元还可以被配置为基于存储器控制器中的存储器应力水平来动态地更新阈值。
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公开(公告)号：US08994741B2
公开(公告)日：2015-03-31
申请号：US13776945
申请日：2013-02-26
Applicant: Apple Inc.
Inventor： Joseph P. Bratt , Peter F. Holland
CPC classification number: G06F12/0215 , G06F12/0802 , G06F12/0862 , G06F12/1027 , G06F12/123 , G06F2212/302 , G06F2212/654
Abstract: In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.
Abstract translation: 在一个实施例中，显示管道包括与显示管正在读取以供显示的图像对应的一个或多个平移单元。 每个翻译单元可以被配置为在图像数据提取之前预取翻译，这可以防止显示管道中的翻译缺失（至少在大多数情况下）。 翻译单元可以以先入先出（FIFO）方式保持翻译，并且显示管取出硬件可以在不再需要给定的翻译或翻译时通知翻译单元。 翻译单元可以使所识别的翻译失效，并且为与最近预取的虚拟页面连续的虚拟页面预取附加翻译。
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Patent Agency Ranking
公开(公告)号：US20150070365A1
公开(公告)日：2015-03-12
申请号：US14019909
申请日：2013-09-06
Applicant: Apple Inc.
Inventor： Peter F. Holland , Albert C. Kuo , Hao Chen
CPC classification number: G06T1/20
Abstract: Embodiments of an apparatus and method are disclosed that may allow for arbitrating multiple read requests to fetch pixel data from a memory. The apparatus may include a first and a second processing pipeline, and a control unit. Each of the processing pipelines may be configured to generate a plurality of read requests to fetch a respective one of a plurality of portions of stored pixel data. The control unit may be configured to determine a priority for each read request dependent upon display coordinates of one or more pixels corresponding to each of the plurality of portions of stored pixel data, and determine an order for the plurality of read requests dependent upon the determined priority for each read request.
Abstract translation: 公开了可以允许仲裁多个读取请求以从存储器获取像素数据的装置和方法的实施例。 该装置可以包括第一和第二处理流水线以及控制单元。 每个处理流水线可以被配置为产生多个读取请求以获取存储的像素数据的多个部分中的相应一个。 控制单元可以被配置为根据与存储的像素数据的多个部分中的每一个相对应的一个或多个像素的显示坐标来确定每个读取请求的优先级，并且根据所确定的多个读取请求确定多个读取请求的顺序 每个读取请求的优先级。
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公开(公告)号：US20150042659A1
公开(公告)日：2015-02-12
申请号：US13963511
申请日：2013-08-09
Applicant: Apple Inc.
Inventor： Peter F. Holland , Brijesh Tripathi
CPC classification number: G09G5/006 , G06T3/4092 , G06T9/00 , G09G2340/02 , G09G2340/0407 , H04N19/124 , H04N19/134 , H04N19/182 , H04N19/184 , H04N19/186 , H04N19/90
Abstract: A method and device for data compression are presented, in which a data processor may receive a packet of image data which includes four groups of N bits, where N is an integer greater than 2. The data processor may compress the received packet of data, such that a total number of bits for the converted packet is less than four times N. The data processor may compress the received packet of image data by reducing the resolution of three of the values while maintaining the resolution of the fourth value. To reduce the resolution of the three values, the data processor may apply a dithering formula to the values. The data processor may then send the converted packet via an interface.
Abstract translation: 提出了一种用于数据压缩的方法和装置，其中数据处理器可以接收包括四个N位组的图像数据分组，其中N是大于2的整数。数据处理器可以压缩所接收的数据分组， 使得转换的分组的总比特数小于N倍。数据处理器可以通过在保持第四值的分辨率的同时降低三个值的分辨率来压缩接收的图像数据分组。 为了降低三个值的分辨率，数据处理器可以对该值应用抖动公式。 然后，数据处理器可以经由接口发送经转换的分组。
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118.发明申请Multiple Quality of Service (QoS) Thresholds or Clock Gating Thresholds Based on Memory Stress Level 有权基于内存应力水平的多种服务质量（QoS）阈值或时钟门控阈值公开(公告)号：US20140240332A1
公开(公告)日：2014-08-28
申请号：US13775641
申请日：2013-02-25
Applicant: APPLE INC.
Inventor： Peter F. Holland , Marc A. Schaub
IPC: G06T1/60
CPC classification number: G06T1/60
Abstract: In an embodiment, a display control unit is configured to transmit read operations to the memory in the system to read image data for processing, and may employ QoS levels with the read operations to ensure that enough data is provided to satisfy the real time display requirements. To determine which QoS level to use for a given read request, the display control unit may be configured to compare an amount of image data in the display control unit (e.g. in various input and/or output buffers in the display control unit) to one or more thresholds. The display control unit may also be configured to dynamically update the thresholds based on a memory stress level in the memory controller.
Abstract translation: 在一个实施例中，显示控制单元被配置为向系统中的存储器发送读取操作以读取用于处理的图像数据，并且可以采用具有读取操作的QoS等级来确保提供足够的数据以满足实时显示要求 。 为了确定对于给定的读取请求使用哪个QoS级别，显示控制单元可以被配置为将显示控制单元中的图像数据量（例如，在显示控制单元中的各种输入和/或输出缓冲器中）与一个 或更多阈值。 显示控制单元还可以被配置为基于存储器控制器中的存储器应力水平来动态地更新阈值。
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公开(公告)号：US20140204100A1
公开(公告)日：2014-07-24
申请号：US13744637
申请日：2013-01-18
Applicant: APPLE INC.
Inventor： Peter F. Holland
IPC: G06T1/20
Abstract: In an embodiment, a display pipe processes video data for visual display. The display pipe may read the video data from memory, and may employ QoS levels with the memory requests to ensure that enough data is provided to satisfy the real time display requirements. The display pipe may include a pixel buffer that stores pixels that are ready for display. Additionally, the display pipe may include one or more input buffers configured to store input video data to be processed and/or one or more output buffers configured to store processed data that is ready for blending into the final pixels for display. The display pipe determine a number of output equivalent pixels in the data in the input and output buffers, and may consider those pixels as well as the ready pixels in the pixel buffer in determining the QoS levels for requests.
Abstract translation: 在一个实施例中，显示管处理用于视觉显示的视频数据。 显示管道可以从存储器读取视频数据，并且可以使用具有存储器请求的QoS级别来确保提供足够的数据以满足实时显示要求。 显示管可以包括存储准备显示的像素的像素缓冲器。 此外，显示管道可以包括被配置为存储要处理的输入视频数据的一个或多个输入缓冲器和/或被配置为存储处理后的数据的一个或多个输出缓冲器，该处理后的数据准备好进行混合到最终的像素中进行显示。 显示管确定输入和输出缓冲器中的数据中的输出等效像素的数量，并且可以在确定请求的QoS等级时考虑像素缓冲器中的那些像素以及就绪像素。
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公开(公告)号：US20140139535A1
公开(公告)日：2014-05-22
申请号：US14163326
申请日：2014-01-24
Applicant: Apple Inc.
Inventor： Joseph P. Bratt , Peter F. Holland , Shing Horng Choo , Timothy J. Millet , Brijesh Tripathi
IPC: G06T1/60
Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.
Abstract translation: 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。
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