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    Apparatuses, methods, and systems for instructions to compartmentalize code
    111.
    发明授权
    Apparatuses, methods, and systems for instructions to compartmentalize code 有权

    公开(公告)号：US11556341B2

    公开(公告)日：2023-01-17

    申请号：US17341068

    申请日：2021-06-07

    Applicant: Intel Corporation

    Inventor： Ravi Sahita ,  Deepak Gupta ,  Vedvyas Shanbhogue ,  David Hansen ,  Jason W. Brandt ,  Joseph Nuzman ,  Mingwei Zhang

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/14

    Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described. In one embodiment, a compartment manager circuit is to determine, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory, load a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory, check if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment, and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core.

    COMPRESSED CACHE MEMORY WITH DECOMPRESS ON FAULT
    113.
    发明申请
    COMPRESSED CACHE MEMORY WITH DECOMPRESS ON FAULT 有权

    公开(公告)号：US20220197793A1

    公开(公告)日：2022-06-23

    申请号：US17130632

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Vedvyas Shanbhogue ,  Jayesh Gaur ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Utkarsh Kakaiya

    IPC: G06F12/0802

    Abstract: An embodiment of an integrated circuit may comprise, coupled to a core, a hardware decompression accelerator, a compressed cache, a processor and communicatively coupled to the hardware decompression accelerator and the compressed cache, and memory and communicatively coupled to the processor, wherein the memory stores microcode instructions which when executed by the processor causes the processor to store a first address to a decompression work descriptor, retrieve a second address where a compressed page is stored in the compressed cache from the decompression work descriptor at the first address in response to an indication of a page fault, and send instructions to the hardware decompression accelerator to decompress the compressed page at the second address. Other embodiments are disclosed and claimed.

    USER TIMER DIRECTLY PROGRAMMED BY APPLICATION
    114.
    发明申请
    USER TIMER DIRECTLY PROGRAMMED BY APPLICATION 有权

    公开(公告)号：US20220147393A1

    公开(公告)日：2022-05-12

    申请号：US17212977

    申请日：2021-03-25

    Applicant: Intel Corporation

    Inventor： Rajesh Sankaran ,  Gilbert Neiger ,  Vedvyas Shanbhogue ,  David Koufaty

    IPC: G06F9/50 ,  G06F9/48

    Abstract: An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include a field for an identifier of a first source operand, a field for an identifier of a destination operand, and a field for an opcode, the opcode to indicate execution circuitry is to program a user timer, and execution circuitry to execute the decoded instruction according to the opcode to retrieve timer program information from a location indicated by the first source operand, and program a user timer indicated by the destination operand based on the retrieved timer program information. Other embodiments are disclosed and claimed.

    Processor extensions to protect stacks during ring transitions
    116.
    发明授权
    Processor extensions to protect stacks during ring transitions 有权

    公开(公告)号：US11176243B2

    公开(公告)日：2021-11-16

    申请号：US16585373

    申请日：2019-09-27

    Applicant: Intel Corporation

    Inventor： Vedvyas Shanbhogue ,  Jason W. Brandt ,  Ravi L. Sahita ,  Barry E. Huntley ,  Baiju V. Patel ,  Deepak K. Gupta

    IPC: G06F21/52 ,  G06F3/06 ,  G06F12/14 ,  G06F9/30 ,  G06F9/46

    Abstract: A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

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