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111.发明授权Interprocessor communication system for direct processor to processor communication between internal general purpose registers transparent to the execution of processors thereof 失效处理器间通信系统，用于直接处理器与内部通用寄存器之间的处理器通信，对其处理器的执行透明
公开(公告)号：US5440689A
公开(公告)日：1995-08-08
申请号：US161858
申请日：1993-12-03
IPC分类号： G06F13/38 , G06F15/16 , G06F15/17 , G06F15/177
CPC分类号： G06F15/17
摘要： A system for direct interprocessor communication in a multiprocessor data processing environment. The system utilizes conventional direct data transfer means and existing I/O port instruction capabilities available on most microprocessors. A destination processor requiring data from one of a source processor's internal registers generates a unique address which specifies the register containing the required data. The address is sent to the data transfer means, causing the direct transfer of data from the designated source processor internal register to the destination processor. Specific circuitry to accomplish this direct data transfer function is described.
摘要翻译： 一种用于在多处理器数据处理环境中进行直接处理器间通信的系统。 该系统利用传统的直接数据传输手段和大多数微处理器上现有的I / O口指令功能。 要求来自源处理器内部寄存器之一的数据的目标处理器产生一个唯一的地址，该地址指定包含所需数据的寄存器。 地址被发送到数据传输装置，导致数据从指定的源处理器内部寄存器直接传送到目标处理器。 描述完成该直接数据传输功能的具体电路。
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112.发明授权Security-enhanced radio frequency object locator system, method and program storage device 有权安全增强射频对象定位系统，方法和程序存储设备公开(公告)号：US08823491B2
公开(公告)日：2014-09-02
申请号：US13348866
申请日：2012-01-12
CPC分类号： G08B21/24
摘要： Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.
摘要翻译： 公开了一种对象定位器系统，方法和程序存储装置。 在实施例中，射频识别（RFID）标签位于限定区域内的对象上，并且每个RFID标签可由RF激活信号激活。 当从特定用户接收到用于定位特定对象的请求（例如，语言或密钥请求）时，验证定位对象的所需许可证，并且可选地，特定用户的身份被认证。 一旦验证了所需许可并且认证了特定用户的身份，三个RFID读取器中的一个发送RF激活信号。 使用从特定对象的RFID标签在三个RFID读取器处接收的RF响应信号来对特定对象的位置进行三角测量。 一旦确定，将位置（例如，通过地图显示，口头消息或文本消息）传达给特定用户。
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公开(公告)号：US08575964B2
公开(公告)日：2013-11-05
申请号：US13426776
申请日：2012-03-22
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
IPC分类号： H03K19/00
CPC分类号： H03K19/0966 , H03K19/0013
摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.
摘要翻译： 电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。 当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。 本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中 只有在本地逻辑设备中已经满足设置时间之后）。 这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。
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114.发明申请SECURITY-ENHANCED RADIO FREQUENCY OBJECT LOCATOR SYSTEM, METHOD AND PROGRAM STORAGE DEVICE 有权安全增强无线电频率对象定位系统，方法和程序存储设备公开(公告)号：US20130181838A1
公开(公告)日：2013-07-18
申请号：US13348866
申请日：2012-01-12
IPC分类号： G08B13/14
CPC分类号： G08B21/24
摘要： Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.
摘要翻译： 公开了一种对象定位器系统，方法和程序存储装置。 在实施例中，射频识别（RFID）标签位于限定区域内的对象上，并且每个RFID标签可由RF激活信号激活。 当从特定用户接收到用于定位特定对象的请求（例如，语言或密钥请求）时，验证定位对象所需的许可，并且可选地，特定用户的身份被认证。 一旦验证了所需许可并且认证了特定用户的身份，三个RFID读取器中的一个发送RF激活信号。 使用从特定对象的RFID标签在三个RFID读取器处接收的RF响应信号来对特定对象的位置进行三角测量。 一旦确定，将位置（例如，通过地图显示，口头消息或文本消息）传达给特定用户。
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115.发明申请ASYNCHRONOUS CIRCUIT WITH AN AT-SPEED BUILT-IN SELF-TEST (BIST) ARCHITECTURE 有权具有快速内置自检（BIST）架构的异步电路公开(公告)号：US20130159803A1
公开(公告)日：2013-06-20
申请号：US13327847
申请日：2011-12-16
IPC分类号： G01R31/28
CPC分类号： G01R31/31813 , G01R31/3187
摘要： Disclosed are embodiments of an integrated circuit that incorporates an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. In the embodiments, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal. Optionally, a time constraint can be added to the capture of the output test data to allow for detection of delay faults.
摘要翻译： 公开了集成电路的实施例，该集成电路结合具有内置自检（BIST）架构的异步电路，使用用于高速测试的握手协议来检测卡住故障。 在实施例中，测试模式发生器将测试模式应用于异步电路，分析器分析输出测试数据。 握手协议通过使用单个脉冲发生器来实现，该单个脉冲发生器向测试模式发生器施加单个脉冲以强制测试模式请求信号的切换，从而控制测试模式对异步电路的应用和随后的切换 的测试模式确认信号。 可以通过切换测试模式确认信号来强制产生该单个脉冲。 可选地，可以将时间约束添加到捕获输出测试数据以允许检测延迟故障。
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公开(公告)号：US08341428B2
公开(公告)日：2012-12-25
申请号：US11767545
申请日：2007-06-25
IPC分类号： G06F21/00
CPC分类号： G06F21/567
摘要： A system and method for protecting computing systems, and more particularly a system and method which a dedicated hardware component configured to communicate with a protection program. A computer hardware subsystem includes a memory comprising content. The content is at least a list of files which have been modified within a predetermined period of time. The list of files is a subset of files of a hard drive. A dedicated hardware component is configured to track the files which have been modified and provide a location of the files to the memory. A communication link between the dedicated hardware component and a protection program provides the protection program with the subset of files of the hard drive as referenced by the memory content.
摘要翻译： 一种用于保护计算系统的系统和方法，更具体地，涉及配置成与保护程序进行通信的专用硬件组件的系统和方法。 计算机硬件子系统包括包含内容的存储器。 内容至少是在预定时间段内被修改的文件的列表。 文件列表是硬盘驱动器文件的一部分。 专用硬件组件被配置为跟踪已被修改的文件并且将文件的位置提供给存储器。 专用硬件组件和保护程序之间的通信链路为保护程序提供硬盘驱动器的文件的子集，如存储器内容所引用的。
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117.发明授权公开(公告)号：US08279861B2
公开(公告)日：2012-10-02
申请号：US12633149
申请日：2009-12-08
申请人： Chi-Chuen Chao-Suren , Ezran D. B. Hall , Pascal A. Nsame , Aydin Suren , Sebastian T. Ventrone
发明人： Chi-Chuen Chao-Suren , Ezran D. B. Hall , Pascal A. Nsame , Aydin Suren , Sebastian T. Ventrone
CPC分类号： G06F17/289 , H04L12/1827 , H04L65/1056 , H04L65/1069 , H04L65/605 , H04L65/607 , H04M3/42391 , H04M3/56 , H04M2203/2061
摘要： A computer-implemented method and system of enabling concurrent real-time multi-language communication between multiple participants using a selective broadcast protocol, the method including receiving at a first server a real-time communication from a first participant, the real-time communication being addressed to a second participant constructed in a first spoken language. A preferred spoken language of receipt of real-time communication is identified by the second participant. A determination is made whether the preferred spoken language of receipt is different than that of the first spoken language of the real-time communication. The real-time communication from the first spoken language is translated and delivered to the preferred spoken language of receipt of the second participant to create a translated real-time communication whenever the preferred spoken language is different than the first spoken language and forwarded without translation when the preferred spoken language of the second participant is the same as the preferred spoken language of the first participant.
摘要翻译： 一种使用选择性广播协议实现多个参与者之间的并发实时多语言通信的计算机实现的方法和系统，所述方法包括在第一服务器处接收来自第一参与者的实时通信，所述实时通信是 致力于以第一语言构建的第二参与者。 由第二参与者确定接收实时通信的首选语言。 确定接收的首选语言是否与实时通信的第一语言的语言不同。 当首选语言不同于第一语言时，来自第一语言的实时通信被翻译并且被传递到接收第二参与者的首选语言以便创建翻译的实时通信，并且在没有翻译的情况下转发 第二参与者的首选语言与第一参与者的首选语言相同。
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118.发明申请公开(公告)号：US20120084540A1
公开(公告)日：2012-04-05
申请号：US13325307
申请日：2011-12-14
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3237 , G06F1/3243 , G06F9/3859 , G06F9/3873
摘要： A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
摘要翻译： 体现在设计过程中使用的机器可读，非暂时性存储介质中的设计结构包括用于动态地改变计算设备的流水线深度的系统。 该系统包括状态机，其基于要执行的处理功能来确定流水线架构的最佳长度。 响应于状态机的流水线序列控制器基于最佳长度改变管道的深度。 多个时钟分离器元件，每个与流水线架构中相应的多个锁存级相关联，并被连接到流水线序列控制器，并适于在功能模式，一个或多个时钟选通模式和直通冲洗 模式。 对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。
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119.发明授权Structure for dynamically adjusting pipelined data paths for improved power management 有权用于动态调整流水线数据路径以改善电源管理的结构公开(公告)号：US08086832B2
公开(公告)日：2011-12-27
申请号：US11869216
申请日：2007-10-09
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3237 , G06F1/3243 , G06F9/3859 , G06F9/3873
摘要： A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
摘要翻译： 体现在设计过程中使用的机器可读，非暂时性存储介质中的设计结构包括用于动态地改变计算设备的流水线深度的系统。 该系统包括状态机，其基于要执行的处理功能来确定流水线架构的最佳长度。 响应于状态机的流水线序列控制器基于最佳长度改变管道的深度。 多个时钟分离器元件，每个与流水线架构中相应的多个锁存级联相关联，连接到流水线序列控制器，并且适于在功能模式，一个或多个时钟选通模式和直通冲洗 模式。 对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。
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120.发明授权公开(公告)号：US07882334B2
公开(公告)日：2011-02-01
申请号：US11276236
申请日：2006-02-20
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
CPC分类号： G06F9/3869 , G11C27/026
摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
摘要翻译： 公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。
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