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    Obscuring memory access patterns in conjunction with deadlock detection or avoidance
    112.
    发明授权
    Obscuring memory access patterns in conjunction with deadlock detection or avoidance 有权

    公开(公告)号：US09524240B2

    公开(公告)日：2016-12-20

    申请号：US13782416

    申请日：2013-03-01

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Gad Sheaffer ,  Shlomo Raikin

    IPC: G06F12/14 ,  G06F12/08 ,  G06F21/55 ,  H04L9/00

    CPC classification number: G06F12/0808 ,  G06F12/0802 ,  G06F21/556 ,  G06F2201/885 ,  G06F2212/1052 ,  H04L9/003

    Abstract: Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.

    SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    113.
    发明申请
    SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权
    SM3 HASH算法加速处理器，方法，系统和指令

    公开(公告)号：US20160070931A1

    公开(公告)日：2016-03-10

    申请号：US14477552

    申请日：2014-09-04

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Vlad Krasnov

    IPC: G06F21/72 ,  G06F9/30

    CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3895 ,  G09C1/00 ,  H04L2209/125

    Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.

    Abstract translation: 处理器包括解码单元，用于解码SM3两轮状态字更新指令。 该指令是指示一个或多个源打包数据操作数。 源压缩数据操作数将具有与SM3哈希算法的一个圆（j）相对应的8个32位状态字Aj，Bj，Cj，Dj，Ej，Fj，Gj和Hj。 源压缩数据操作数还具有足以评估两轮SM3哈希算法的一组消息。 与解码单元耦合的执行单元可响应于该指令而在一个或多个目的地存储位置中存储一个或多个结果打包数据操作数。 结果打包数据操作数将具有至少四个二轮更新的32位状态字Aj + 2，Bj + 2，Ej + 2和Fj + 2，它们对应于一个圆（j + 2）的SM3哈希算法。

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