公开(公告)号：US20230197689A1

公开(公告)日：2023-06-22

申请号：US18169735

申请日：2023-02-15

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/49827 ,  H01L21/563 ,  H01L23/3114 ,  H01L2021/60037

Abstract: A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.

公开(公告)号：US11587895B2

公开(公告)日：2023-02-21

申请号：US17236425

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Semiconductor devices having interconnect structures with vertically offset bonding surfaces, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate at least partially covered by a first dielectric material having an upper surface, and an interconnect structure extending therefrom. The interconnect structure can include a plurality of conductive elements, and a continuous region of a first insulating material at least partially between the plurality of conductive elements. The plurality of conductive elements and the continuous region can have coplanar end surfaces. The interconnect structure can further include a perimeter structure at least partially surrounding the plurality of conductive elements and the continuous region. The perimeter structure can have an uppermost surface that can be vertically offset from the upper surface of the first dielectric material and/or the coplanar end surfaces.

公开(公告)号：US11527436B2

公开(公告)日：2022-12-13

申请号：US16902115

申请日：2020-06-15

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/306 ,  H01L21/311

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

公开(公告)号：US20220157728A1

公开(公告)日：2022-05-19

申请号：US17588694

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/538 ,  G11C5/02 ,  G11C5/06 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory controller die—e.g., high-bandwidth memory. Further, a processing unit (e.g., a processor) may be attached to the memory controller die without an interposer to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. In addition, the semiconductor memory stack and the processing unit can be attached to a package substrate without an interposer.

公开(公告)号：US20220068820A1

公开(公告)日：2022-03-03

申请号：US17325090

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/538 ,  H01L27/06 ,  H01L27/092 ,  H01L21/50 ,  H01L21/768

Abstract: Systems and methods for a semiconductor device having a substrate material with a trench at a front side, a conformal dielectric material over at least a portion of the front side of the substrate material and in the trench, a fill dielectric material on the conformal dielectric material in the trench, and a conductive portion formed during front-end-of-line (FEOL) processing. The conductive portion may include an FEOL interconnect via extending through the fill dielectric material and at least a portion of the conformal dielectric material and having a front side portion defining a front side electrical connection extending beyond the front side of the semiconductor substrate material and a backside portion defining an active contact surface. The conductive portion may extend across at least a portion of the conformal dielectric material and the fill dielectric material and have a backside surface defining an active contact surface.

公开(公告)号：US20220068765A1

公开(公告)日：2022-03-03

申请号：US17325122

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: Systems and methods for a semiconductor device having a front-end-of-line structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor substrate material and a front side, and an interconnect structure extending through the dielectric material. The interconnect structure may be electrically connected to a semiconductor memory array proximate the front side of the dielectric material. The semiconductor device may further have an insulating material encasing at least a portion of the semiconductor memory array and an opening created during back-end-of-line processing through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

公开(公告)号：US11195740B2

公开(公告)日：2021-12-07

申请号：US16386517

申请日：2019-04-17

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Kyle K. Kirby

IPC: H01L21/683 ,  H01L23/48 ,  H01L21/306

Abstract: An assembly comprising a device wafer received in a recess of a carrier wafer. A device wafer comprising a protrusion terminating at an active surface bearing integrated circuitry, the protrusion surrounded by a peripheral flat extending to an outer periphery of the device wafer. A method of wafer thinning using the previously described carrier wafer and device wafer. Various implementations of a carrier wafer having a recess are also disclosed, as are methods of fabrication.

公开(公告)号：US11177175B2

公开(公告)日：2021-11-16

申请号：US16055492

申请日：2018-08-06

Applicant: Micron Technology, Inc.

Inventor： William M. Hiatt ,  Kyle K. Kirby

IPC: H01L21/768 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48

Abstract: Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.

公开(公告)号：US20210351163A1

公开(公告)日：2021-11-11

申请号：US17383304

申请日：2021-07-22

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.

公开(公告)号：US20210296289A1

公开(公告)日：2021-09-23

申请号：US17339560

申请日：2021-06-04

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Chao Wen Wang

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/532

Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.