公开(公告)号：US20240289266A1

公开(公告)日：2024-08-29

申请号：US18441775

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F12/02

CPC classification number: G06F12/0223

Abstract: Apparatuses, systems, and methods for adjustable write timing. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent/received across the first terminal and a second set of data and a second set of metadata may be sent/received across the second terminal. When a first setting is enabled, the first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other. When disabled, the metadata may be stored in a single location. A second setting may be used to adjust a write delay to account for different timing when the first setting is enabled vs disabled.

公开(公告)号：US20240289217A1

公开(公告)日：2024-08-29

申请号：US18444482

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1016

Abstract: Apparatuses, systems, and methods for variable input error correction code (ECC) circuits. Different modes of a memory device may involve different numbers of bits of information (e.g., data and/or metadata) being accessed. An ECC input circuit receives the variable number of bits of information and provides a fixed number of input bits. An ECC engine uses the input bits to generate parity (during a write) or to locate errors (during a read). The number of input bits may be based on a number of inputs of the ECC engine. The ECC input circuit may generate filler bits to add to the bits of information to generate the input bits.

公开(公告)号：US20240281327A1

公开(公告)日：2024-08-22

申请号：US18441830

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Scott E. Smith

IPC: G06F11/10 ,  G06F11/14 ,  G06F13/16

CPC classification number: G06F11/1068 ,  G06F11/1435 ,  G06F13/1673

Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, both the metadata and the data may be provided to an error correction code circuit as a combined code word that provides error correction for both the data and the metadata.

公开(公告)号：US20240274220A1

公开(公告)日：2024-08-15

申请号：US18505532

申请日：2023-11-09

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C29/52 ,  G11C5/02

CPC classification number: G11C29/52 ,  G11C5/02

Abstract: Systems, methods, and apparatuses related to determining a number of access line contacts for an access line in a memory device are described. An apparatus includes a first data plane, a second data plane, and a sub-access line driver (SAD), all coupled to a local access line. A first portion of the local access line between the SAD and the first data plane includes a first number of access line contacts, a second portion of the local access line between the SAD and the second data plane includes a second number of access line contacts, and the first number of access line contacts are determined by data corresponding to a first function of the first data plane and the second number of access line contacts are determined by data corresponding to a second function of the data plane.

公开(公告)号：US20240272984A1

公开(公告)日：2024-08-15

申请号：US18431232

申请日：2024-02-02

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/10 ,  G06F12/02

CPC classification number: G06F11/1076 ,  G06F12/0223

Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

公开(公告)号：US20240272979A1

公开(公告)日：2024-08-15

申请号：US18431306

申请日：2024-02-02

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/10

CPC classification number: G06F11/1004

Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

公开(公告)号：US20240256380A1

公开(公告)日：2024-08-01

申请号：US18424282

申请日：2024-01-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/10

CPC classification number: G06F11/1004

Abstract: Apparatuses, systems, and methods for bounded fault compliant metadata storage. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent/received across the first terminal and a second set of data and a second set of metadata may be sent/received across the second terminal. The first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other.

公开(公告)号：US20240170088A1

公开(公告)日：2024-05-23

申请号：US18504302

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Scott E. Smith ,  Sujeet Ayyapureddi

IPC: G11C29/42

CPC classification number: G11C29/42

Abstract: Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

公开(公告)号：US20240161856A1

公开(公告)日：2024-05-16

申请号：US18504324

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Scott E. Smith ,  Sujeet Ayyapureddi

IPC: G11C29/42 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C2029/1204

Abstract: Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

公开(公告)号：US20240160351A1

公开(公告)日：2024-05-16

申请号：US18504362

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Scott E. Smith

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0634 ,  G06F3/0673

Abstract: Apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. A memory array is divided into column planes and an extra column plane. In some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. The extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.