公开(公告)号：US20230013333A1

公开(公告)日：2023-01-19

申请号：US17950968

申请日：2022-09-22

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/11507 ,  H01L27/108 ,  H01L27/11504 ,  H01L49/02 ,  H01L21/768

Abstract: A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes. Upper capacitor electrode material is formed over the capacitor insulator and the lower capacitor electrodes. A horizontally-elongated conductive line is formed atop individual of the groups that directly electrically couple together the upper capacitor electrode material there-below in that individual group

公开(公告)号：US20230005903A1

公开(公告)日：2023-01-05

申请号：US17364476

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh

IPC: H01L25/18 ,  H01L27/108 ,  H01L25/00 ,  H01L23/00

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.

公开(公告)号：US20220399308A1

公开(公告)日：2022-12-15

申请号：US17344444

申请日：2021-06-10

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Yuan He

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

公开(公告)号：US20220375930A1

公开(公告)日：2022-11-24

申请号：US17326286

申请日：2021-05-20

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H01L27/06 ,  G11C5/06 ,  H01L23/538 ,  H01L27/092 ,  H01L21/8238 ,  H01L25/065

Abstract: Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.

公开(公告)号：US11476262B2

公开(公告)日：2022-10-18

申请号：US16941174

申请日：2020-07-28

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/11507 ,  H01L27/11504 ,  H01L21/768 ,  H01L49/02 ,  H01L27/108

Abstract: A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes. Upper capacitor electrode material is formed over the capacitor insulator and the lower capacitor electrodes. A horizontally-elongated conductive line is formed atop individual of the groups that directly electrically couple together the upper capacitor electrode material there-below in that individual group.

公开(公告)号：US20220131003A1

公开(公告)日：2022-04-28

申请号：US17568133

申请日：2022-01-04

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Steve V. Cole ,  Scott J. Derner ,  Toby D. Robbs

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11587 ,  G11C11/22 ,  G11C11/4091

Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

公开(公告)号：US20220037342A1

公开(公告)日：2022-02-03

申请号：US16941174

申请日：2020-07-28

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/11507 ,  H01L27/11504 ,  H01L27/108 ,  H01L49/02

Abstract: A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes. Upper capacitor electrode material is formed over the capacitor insulator and the lower capacitor electrodes. A horizontally-elongated conductive line is formed atop individual of the groups that directly electrically couple together the upper capacitor electrode material there-below in that individual group

公开(公告)号：US11171206B2

公开(公告)日：2021-11-09

申请号：US16509093

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey ,  Chandra V. Mouli ,  John A. Smythe, III

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/762

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

公开(公告)号：US11114443B2

公开(公告)日：2021-09-07

申请号：US16555565

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Fatma Arzum Simsek-Ege ,  Sanjeev Sapra ,  Thomas A. Figura ,  Kangle Li

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/67 ,  H01L21/762

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.

公开(公告)号：US11094697B2

公开(公告)日：2021-08-17

申请号：US16183468

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C11/403 ,  H01L49/02 ,  H01L29/423 ,  H01L29/78 ,  H01L23/528 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.