公开(公告)号：US10157926B2

公开(公告)日：2018-12-18

申请号：US15664161

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  H01L29/78 ,  G11C11/403 ,  H01L23/528 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US20180061835A1

公开(公告)日：2018-03-01

申请号：US15664161

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/423 ,  H01L49/02 ,  H01L29/78

CPC classification number: H01L27/108 ,  G11C11/403 ,  H01L23/528 ,  H01L27/0688 ,  H01L28/90 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/7827

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US11094697B2

公开(公告)日：2021-08-17

申请号：US16183468

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C11/403 ,  H01L49/02 ,  H01L29/423 ,  H01L29/78 ,  H01L23/528 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US20190326292A1

公开(公告)日：2019-10-24

申请号：US16459956

申请日：2019-07-02

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C11/405 ,  G11C5/06

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20180301454A1

公开(公告)日：2018-10-18

申请号：US16006301

申请日：2018-06-12

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum SImsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/405 ,  G11C11/401

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US10079235B2

公开(公告)日：2018-09-18

申请号：US15664183

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/401

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20180061836A1

公开(公告)日：2018-03-01

申请号：US15664183

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US10361204B2

公开(公告)日：2019-07-23

申请号：US16006301

申请日：2018-06-12

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Slmsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/405 ,  G11C11/401

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20190088652A1

公开(公告)日：2019-03-21

申请号：US16183468

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  G11C11/403 ,  H01L29/78 ,  H01L29/10 ,  H01L27/06 ,  H01L29/08 ,  H01L23/528

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.