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公开(公告)号:US11631740B2
公开(公告)日:2023-04-18
申请号:US17097410
申请日:2020-11-13
Applicant: Micron Technology, Inc.
Inventor: John D. Hopkins , Nancy M. Lomeli
IPC: H01L27/11582 , H01L29/10 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11556
Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. A ring is around individual of the channel-material strings in at least one of a lowest of the conductive tiers or a lowest of the insulative tiers. Individual of the rings have a top that is below all of the memory cells. Other embodiments are disclosed.
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公开(公告)号:US20230099418A1
公开(公告)日:2023-03-30
申请号:US18076702
申请日:2022-12-07
Applicant: Micron Technology, Inc.
Inventor: Daniel Billingsley , Jordan D. Greenlee , John D. Hopkins , Yongjun Jeff Hu , Swapnil Lengade
IPC: H01L27/11556 , H01L27/11582 , H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11565 , G11C16/04
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号:US11616075B2
公开(公告)日:2023-03-28
申请号:US17156241
申请日:2021-01-22
Applicant: Micron Technology, Inc.
Inventor: John D. Hopkins , David Daycock
IPC: H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/10
Abstract: A method that is part of a method of forming an elevationally-extending string of memory cells comprises forming an intervening structure that is elevationally between upper and lower stacks that respectively comprise alternating tiers comprising different composition materials. The intervening structure is formed to comprise an elevationally-extending-dopant-diffusion barrier and laterally-central material that is laterally inward of the dopant-diffusion barrier and has dopant therein. Some of the dopant is thermally diffused from the laterally-central material into upper-stack-channel material. The dopant-diffusion barrier during the thermally diffusing is used to cause more thermal diffusion of said dopant into the upper-stack-channel material than diffusion of said dopant, if any, into lower-stack-channel material. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号:US20230062084A1
公开(公告)日:2023-03-02
申请号:US17475057
申请日:2021-09-14
Applicant: Micron Technology, Inc.
Inventor: John D. Hopkins , Haoyu Li
IPC: H01L27/11582 , H01L27/11556
Abstract: A memory array comprising strings of memory cells comprises conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprising a vertical stack comprises alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. Other embodiments, including method, are disclosed.
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公开(公告)号:US20230061327A1
公开(公告)日:2023-03-02
申请号:US18047245
申请日:2022-10-17
Applicant: Micron Technology, Inc.
Inventor: John D. Hopkins , Jordan D. Greenlee , Nancy M. Lomeli
IPC: H01L27/11556 , H01L27/11582 , H01L23/538 , G11C5/06 , G11C5/02 , H01L27/11575
Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.
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公开(公告)号:US20230055422A1
公开(公告)日:2023-02-23
申请号:US17409476
申请日:2021-08-23
Applicant: Micron Technology, Inc.
Inventor: Jordan D. Greenlee , John D. Hopkins , M. Jared Barclay , Andrew Li , Aireus Christensen
IPC: G11C16/04 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11582 , H01L27/1157 , H01L27/11565
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.
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公开(公告)号:US20230054920A1
公开(公告)日:2023-02-23
申请号:US17409434
申请日:2021-08-23
Applicant: Micron Technology, Inc.
Inventor: John D. Hopkins , Jordan D. Greenlee
IPC: H01L27/11582 , H01L27/11556
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material-string constructions that extend through the insulative tiers and the conductive tiers into the conductor tier. The channel material of the channel-material-string constructions directly electrically couples to conductor material of the conductor tier. The conductor tier comprises islands comprising material of different composition from that of the conductor material of the conductor tier that surrounds individual of the islands. The islands are directly against bottoms of the channel-material-string constructions. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other aspects, including method, are disclosed.
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公开(公告)号:US20230054054A1
公开(公告)日:2023-02-23
申请号:US17409355
申请日:2021-08-23
Applicant: Micron Technology, Inc.
Inventor: Alyssa N. Scarbrough , John D. Hopkins , Jordan D. Greenlee
IPC: G11C16/04 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11565 , H01L27/11582
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. The insulative tier immediately-above a lowest of the conductive tiers comprises a lower first insulating material and an upper second insulating material above the upper first insulating material. The upper second insulating material is of different composition from that of the lower first insulating material. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other embodiments, including method, are disclosed.
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公开(公告)号:US11574870B2
公开(公告)日:2023-02-07
申请号:US16990518
申请日:2020-08-11
Applicant: Micron Technology, Inc.
Inventor: John D. Hopkins , Jordan D. Greenlee , Marko Milojevic
IPC: H01L23/532 , H01L23/522 , H01L27/146 , H01L27/11556 , H01L27/11524 , H01L45/00 , H01L21/762 , H04N21/422 , H04N21/21 , H01L27/11521
Abstract: A microelectronic device comprises pillar structures extending vertically through an isolation material, conductive lines electrically coupled to the pillar structures, contact structures between the pillar structures and the conductive lines, and interconnect structures between the conductive lines and the contact structures. The conductive lines comprise one or more of titanium, ruthenium, aluminum, and molybdenum. The interconnect structures comprise a material composition that is different than one or more of a material composition of the contact structures and a material composition of the conductive lines. Related memory devices, electronic systems, and methods are also described.
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公开(公告)号:US20230005956A1
公开(公告)日:2023-01-05
申请号:US17941900
申请日:2022-09-09
Applicant: Micron Technology, Inc.
Inventor: John D. Hopkins , Justin D. Shepherdson , Collin Howder , Jordan D. Greenlee
IPC: H01L27/11582 , H01L27/11556 , H01L21/02 , H01L27/11565 , H01L21/311 , H01L21/285 , H01L27/11519 , H01L29/66 , H01L21/28
Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.
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