公开(公告)号：US20210064788A1

公开(公告)日：2021-03-04

申请号：US16997661

申请日：2020-08-19

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Liji Gopalakrishnan ,  John Eric Linstadt ,  Steven C. Woo

IPC: G06F21/75 ,  H04L9/00

Abstract: Methods and systems for enabling secure memory transactions in a memory controller are disclosed. Responsive to determining that an incoming request is for a secure memory transaction, the incoming request is placed in a secure request container. The memory container then enters a state where re-ordering between requests for secure memory transactions placed in the secure request container and requests for non-secure memory transactions from other containers is prevented in a scheduling queue.

公开(公告)号：US20210035623A1

公开(公告)日：2021-02-04

申请号：US16999869

申请日：2020-08-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Zhichao Lu ,  Kenneth Lee Wright

IPC: G11C11/4091 ,  G06F11/10 ,  G11C11/4076

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

公开(公告)号：US20210004337A1

公开(公告)日：2021-01-07

申请号：US16942380

申请日：2020-07-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/16 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US10762948B2

公开(公告)日：2020-09-01

申请号：US15829787

申请日：2017-12-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Zhichao Lu ,  Kenneth Lee Wright

IPC: G11C11/34 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/4076

Abstract: Memory devices, controllers and associated methods are provided. In one embodiment, a memory device is provided. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

公开(公告)号：US10678719B2

公开(公告)日：2020-06-09

申请号：US15761746

申请日：2016-09-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright ,  John Eric Linstadt ,  Craig Hampel

IPC: G06F13/16 ,  G06F12/0868 ,  G06F12/0888 ,  G11C7/10 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0895 ,  G06F13/28 ,  G11C29/52

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

公开(公告)号：US10650881B2

公开(公告)日：2020-05-12

申请号：US16440015

申请日：2019-06-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52 ,  G11C29/04

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20200035323A1

公开(公告)日：2020-01-30

申请号：US16537021

申请日：2019-08-09

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/44 ,  G11C29/00 ,  G11C5/04 ,  G11C11/401 ,  G11C29/02 ,  G11C29/52

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US10511276B1

公开(公告)日：2019-12-17

申请号：US16043754

申请日：2018-07-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Carl W. Werner ,  John Eric Linstadt

IPC: H03F1/02 ,  H03F1/30 ,  H03F3/16 ,  H03F19/00 ,  G06N10/00

Abstract: A signal amplifier is distributed between first and second IC devices and includes a low-power input stage disposed within the first IC device, a bias-current source disposed within the second IC device and an output stage disposed within the second IC device. The output stage includes a resistance disposed within the second IC device and having a first terminal coupled to a drain terminal of a transistor within the input stage via a first signaling line that extends between the first and second IC devices.

公开(公告)号：US20190278722A1

公开(公告)日：2019-09-12

申请号：US16243055

申请日：2019-01-08

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F13/16 ,  G06F12/06 ,  G11C7/10 ,  G06F12/02 ,  G11C7/22 ,  G11C7/20

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US20190164588A1

公开(公告)日：2019-05-30

申请号：US16097579

申请日：2017-05-03

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Brent Steven Haukness ,  Kenneth L. Wright ,  Thomas Vogelsang

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/409 ,  G11C11/408

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.