公开(公告)号：US20180138201A1

公开(公告)日：2018-05-17

申请号：US15855074

申请日：2017-12-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daiki NAKAMURA ,  Hisao IKEDA ,  Kouhei TOYOTAKA

IPC: H01L27/12 ,  H01L51/52 ,  H01L27/32

CPC classification number: H01L27/12 ,  H01L27/1255 ,  H01L27/322 ,  H01L27/323 ,  H01L27/3246 ,  H01L27/3251 ,  H01L27/3262 ,  H01L27/3279 ,  H01L51/5218 ,  H01L51/5228 ,  H01L51/5234 ,  H01L51/524 ,  H01L51/5284 ,  H01L2251/301 ,  H01L2251/303 ,  H01L2251/5315 ,  H01L2251/5338

Abstract: To provide a light-emitting device or an input/output device with little unevenness in display luminance or high reliability and to provide an input/output device with high detection sensitivity, a light-emitting device is configured to include a first substrate, a light-emitting element over the first substrate, a first conductive layer over the light-emitting element, a first insulating layer over the first conductive layer, a second conductive layer over the first insulating layer, and a second substrate over the second conductive layer. The light-emitting element includes a first electrode over the first substrate, a layer containing a light-emitting organic compound over the first electrode, and a second electrode over the layer containing a light-emitting organic compound. The second electrode is electrically connected to the first and second conductive layers. The first conductive layer and the second electrode transmit light emitted from the light-emitting element. The resistance of the second conductive layer is lower than that of the second electrode.

公开(公告)号：US20170213851A1

公开(公告)日：2017-07-27

申请号：US15381702

申请日：2016-12-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideaki SHISHIDO ,  Hiroyuki MIYAKE ,  Kouhei TOYOTAKA ,  Makoto KANEYASU

IPC: H01L27/12 ,  H01L33/62 ,  G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/134309 ,  G02F1/134336 ,  G02F1/13624 ,  G02F1/136277 ,  G02F1/136286 ,  G02F2201/52 ,  G09G3/2085 ,  G09G3/3607 ,  G09G3/3611 ,  G09G3/3659 ,  G09G2300/0465 ,  G09G2300/08 ,  H01L27/1255 ,  H01L27/3211 ,  H01L27/3213 ,  H01L27/3216 ,  H01L27/3218 ,  H01L27/323 ,  H01L27/3244 ,  H01L27/3248 ,  H01L27/326 ,  H01L27/3262 ,  H01L27/3276 ,  H01L33/62

Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.

公开(公告)号：US20170131607A1

公开(公告)日：2017-05-11

申请号：US15410043

申请日：2017-01-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiroyuki MIYAKE ,  Kouhei TOYOTAKA

IPC: G02F1/1362 ,  G02F1/1368

CPC classification number: G11C19/28 ,  G02F1/136277 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/0297 ,  H01L27/1225 ,  H01L29/7869

Abstract: To provide a semiconductor device having a high aperture ratio and including a capacitor with a high charge capacitance. To provide a semiconductor device with a narrow bezel. A transistor over a substrate; a first conductive film over a surface over which a gate electrode of the transistor is provided; a second conductive film over a surface over which a pair of electrodes of the transistor is provided; and a first light-transmitting conductive film electrically connected to the first conductive film and the second conductive film are included. The second conductive film overlaps the first conductive film with a gate insulating film of the transistor laid between the second conductive film and the first conductive film.

公开(公告)号：US20170039976A1

公开(公告)日：2017-02-09

申请号：US15300000

申请日：2016-10-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroyuki MIYAKE ,  Kouhei TOYOTAKA

IPC: G09G3/36 ,  G11C19/28 ,  H03K3/356

CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3696 ,  G09G5/18 ,  G09G2300/0404 ,  G09G2300/0413 ,  G09G2310/0205 ,  G09G2310/0286 ,  G09G2310/0291 ,  G11C19/28 ,  H03K3/356026

Abstract: Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.

Abstract translation: 在像素部分的左侧和右侧设置两个包括移位寄存器和包括单导电型晶体管的解复用器的栅极驱动器。 栅极线在每M行中交替连接到左侧和右侧栅极驱动器。 移位寄存器包括串联连接的k个第一单元电路。 解复用器包括k个第二单位电路，其中每个电路从第一单元电路输入信号，并且连接M个栅极线。 第二单元电路选择在M个栅极线之间输出来自第一单位电路的输入信号的一个或多个布线，并将来自第一单元电路的信号输出到所选择的布线。 由于门信号可以从一级移位寄存器的输出输出到M条栅极线，所以移位寄存器的宽度可以变窄。

公开(公告)号：US20160335953A1

公开(公告)日：2016-11-17

申请号：US15221662

申请日：2016-07-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kouhei TOYOTAKA

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G3/20 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021

Abstract: A display device includes a plurality of pulse output circuits each of which outputs signals to one of the two kinds of scan lines and a plurality of inverted pulse output circuits each of which outputs, to the other of the two kinds of scan lines, inverted or substantially inverted signals of the signals output from the pulse output circuits. Each of the plurality of inverted pulse output circuits operates with at least two kinds of signals used for the operation of the plurality of pulse output circuits. Thus, through current generated in the inverted pulse output circuits can be reduced.

Abstract translation: 显示装置包括多个脉冲输出电路，每个脉冲输出电路将信号输出到两种扫描线之一，以及多个反相脉冲输出电路，每个反相脉冲输出电路向两条扫描线中的另一条输出反相或 从脉冲输出电路输出的信号基本反转的信号。 多个反相脉冲输出电路中的每一个以用于多个脉冲输出电路的操作的至少两种信号进行工作。 因此，可以减少在反相脉冲输出电路中产生的电流。

公开(公告)号：US20150316976A1

公开(公告)日：2015-11-05

申请号：US14695797

申请日：2015-04-24

Applicant: Semiconductor Energy Laboratory Co., LTD.

Inventor： Kouhei TOYOTAKA ,  Yuji IWAKI

IPC: G06F1/32 ,  G06F1/16

CPC classification number: G06F1/3265 ,  G06F1/1616 ,  G06F1/1641 ,  G06F1/1643 ,  G06F1/1652 ,  G06F1/1677 ,  G06F1/3287 ,  G06F3/1423 ,  G09G3/3208 ,  G09G2300/0408 ,  G09G2310/0218 ,  Y02D10/153

Abstract: A low-power semiconductor device is provided. The semiconductor device includes a movable portion, a plurality of scan line driver circuits, and a control portion. The movable portion includes a plurality of regions driven by the plurality of scan line driver circuits. One of the scan line driver circuits is electrically connected to another one of the scan line driver circuits adjacent to the scan line driver circuit through a switch. The control portion has a function of supplying a start pulse to one scan line driver circuit selected from the plurality of scan line driver circuits. The movable portion can be folded between the plurality of regions.

Abstract translation: 提供了一种低功率半导体器件。 半导体器件包括可移动部分，多条扫描线驱动电路和控制部分。 可移动部分包括由多个扫描线驱动电路驱动的多个区域。 其中一个扫描线驱动电路通过开关电连接到与扫描线驱动电路相邻的扫描线驱动电路中的另一个。 控制部分具有向从多个扫描线驱动电路中选择的一个扫描线驱动电路提供起始脉冲的功能。 可移动部分可以在多个区域之间折叠。

公开(公告)号：US20140241487A1

公开(公告)日：2014-08-28

申请号：US14185221

申请日：2014-02-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiroyuki MIYAKE ,  Kouhei TOYOTAKA

IPC: H01L27/12 ,  H01L29/786 ,  G11C19/28 ,  H01L29/24

CPC classification number: G11C19/28 ,  G02F1/136277 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/0297 ,  H01L27/1225 ,  H01L29/7869

Abstract: To provide a semiconductor device having a high aperture ratio and including a capacitor with a high charge capacitance. To provide a semiconductor device with a narrow bezel. A transistor over a substrate; a first conductive film over a surface over which a gate electrode of the transistor is provided; a second conductive film over a surface over which a pair of electrodes of the transistor is provided; and a first light-transmitting conductive film electrically connected to the first conductive film and the second conductive film are included. The second conductive film overlaps the first conductive film with a gate insulating film of the transistor laid between the second conductive film and the first conductive film.

Abstract translation: 提供具有高孔径比的半导体器件，并且包括具有高电荷电容的电容器。 提供具有窄边框的半导体器件。 衬底上的晶体管; 在其上提供晶体管的栅电极的表面上的第一导电膜; 在其上提供晶体管的一对电极的表面上的第二导电膜; 并且包括与第一导电膜和第二导电膜电连接的第一透光性导电膜。 第二导电膜与第二导电膜和第一导电膜之间的晶体管的栅极绝缘膜与第一导电膜重叠。

公开(公告)号：US20140240631A1

公开(公告)日：2014-08-28

申请号：US14184996

申请日：2014-02-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideaki SHISHIDO ,  Hiroyuki MIYAKE ,  Seiko INOUE ,  Kouhei TOYOTAKA ,  Koji KUSUNOKI

IPC: G02F1/1362

CPC classification number: G02F1/136286 ,  G02F1/136204 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/66

Abstract: Transistors each include a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A driver circuit portion includes first to third wirings formed in the same step as the gate electrode, fourth to sixth wirings formed in the same step as the source electrode and the drain electrode, a seventh wiring formed in the same step as a pixel electrode, a first region where the second wiring intersects with the fifth wiring, and a second region where the third wiring intersects with the sixth wiring. The first wiring is connected to the fourth wiring through the seventh wiring. A distance between the wirings in the second region is longer than that in the first region.

Abstract translation: 晶体管各自包括栅电极，栅电极上的栅极绝缘层，栅极绝缘层上的氧化物半导体层，以及氧化物半导体层上的源电极和漏电极。 驱动器电路部分包括以与栅电极相同的步骤形成的第一至第三布线，以与源电极和漏电极相同的步骤形成的第四至第六布线，与像素电极在相同步骤中形成的第七布线， 第二布线与第五布线相交的第一区域和第三布线与第六布线相交的第二区域。 第一布线通过第七布线连接到第四布线。 第二区域中的布线之间的距离比第一区域长。

公开(公告)号：US20140027765A1

公开(公告)日：2014-01-30

申请号：US13947741

申请日：2013-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kouhei TOYOTAKA

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L27/1225

Abstract: A highly reliable semiconductor device in which a shift in the threshold voltage of a transistor due to deterioration is prevented is provided. The semiconductor device is formed using a sequential circuit including: a first transistor controlling the electrical connection between a first wiring and a second wiring; a second transistor and a third transistor in each of which a source and a drain are electrically connected to each other and which control the electrical connection between the second wiring and a third wiring; and a switch group controlling the electrical connection between a gate of the first transistor and the third wiring or a fourth wiring, the electrical connection between a gate of the second transistor and the third wiring or the fourth wiring, and the electrical connection between a gate of the third transistor and the third wiring or the fourth wiring in response to a control signal.

Abstract translation: 提供了一种高度可靠的半导体器件，其中防止由于劣化导致的晶体管的阈值电压偏移。 半导体器件使用顺序电路形成，该顺序电路包括：第一晶体管，其控制第一布线和第二布线之间的电连接; 第二晶体管和第三晶体管，其中源极和漏极彼此电连接并且控制第二布线和第三布线之间的电连接; 以及控制第一晶体管的栅极与第三布线或第四布线之间的电连接的开关组，第二晶体管的栅极与第三布线或第四布线之间的电连接以及栅极之间的电连接 的第三晶体管和第三布线或第四布线。

公开(公告)号：US20130278324A1

公开(公告)日：2013-10-24

申请号：US13862932

申请日：2013-04-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Makoto KANEYASU ,  Kouhei TOYOTAKA

IPC: H03K3/012

CPC classification number: H03K3/012 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0842 ,  G09G2310/0291 ,  G09G2330/021

Abstract: A semiconductor device which has reduced power consumption and includes a selection transistor is provided. A semiconductor device in which the number of wirings and terminals for inputting a power supply potential is reduced and which operates at high speed is provided. A buffer circuit connected to a gate line connected to a gate of the selection transistor has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential depending on the selection signal. A bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side among a plurality of inverters included in a buffer circuit. Further, by providing a delay circuit in the buffer circuit, the bootstrap circuit starts to boost a potential at the timing later than the input of the selection signal.

Abstract translation: 提供具有降低的功耗并且包括选择晶体管的半导体器件。 提供了一种半导体装置，其中用于输入电源电位的布线和端子的数量减少并且以高速运行。 连接到与选择晶体管的栅极连接的栅极线的缓冲电路具有通过使用高电源电位产生高于高电源电位的电位并根据选择信号输出电位的功能。 自举电路提高输入到包括在缓冲电路中的多个逆变器中最靠近输出侧的逆变器的高电源电位。 此外，通过在缓冲电路中设置延迟电路，自举电路在比选择信号的输入晚的定时开始提高电位。