-
公开(公告)号：US20200111403A1
公开(公告)日：2020-04-09
申请号：US16263253
申请日：2019-01-31
Inventor： Jinho Kim , Yongsang Kim , Sangmin Shin , Jongsu Oh , Youngki Jung
Abstract: A display panel is provided. In the display panel, a plurality of pixels respectively including a plurality of sub pixels are arranged in a matrix form on a glass. Each of the plurality of sub pixels includes a driving circuit disposed on the glass and configured to receive a PAM data voltage and a PWM data voltage, and an inorganic light emitting device configured to emit a light based on a driving current provided from the driving circuit. The PAM data voltage is applied at once to the plurality of pixels included in the display panel. The driving circuit compensates a deviation between driving circuits included in each of the plurality of sub pixels based on a driving voltage of the driving circuit, and controls a pulse width of a driving current having an amplitude corresponding to the applied PAM data voltage based on the applied PWM data voltage.
-
112.发明授权Three-dimensional nonvolatile memory devices including interposed floating gates 有权三维非易失性存储器件包括插入的浮动栅极公开(公告)号：US09105736B2
公开(公告)日：2015-08-11
申请号：US14164408
申请日：2014-01-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byoungkeun Son , Hansoo Kim , Jinho Kim , Kihyun Kim
IPC: H01L29/66 , H01L21/8238 , H01L29/788 , H01L29/423 , H01L29/78 , H01L27/115
CPC classification number: H01L21/28 , H01L27/11519 , H01L27/11551 , H01L27/11553 , H01L27/11556 , H01L27/11582 , H01L29/42324 , H01L29/42364 , H01L29/66666 , H01L29/66825 , H01L29/7827 , H01L29/7841 , H01L29/788 , H01L29/7883 , H01L29/7889
Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.
Abstract translation: 提供三维非易失性存储器件及其制造方法。 存储器件包括穿透层间绝缘层的半导体柱和交替层叠在衬底上并电连接到衬底的导电层和选择性地插入在半导体柱和导电层之间的浮置栅。 浮动栅极形成在导电层中的凹部中。
-
113.发明申请THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES INCLUDING INTERPOSED FLOATING GATES 审中-公开三维非易失性存储器件，包括插入的浮动门公开(公告)号：US20150145016A1
公开(公告)日：2015-05-28
申请号：US14614908
申请日：2015-02-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byoungkeun Son , Hansoo Kim , Jinho Kim , Kihyun Kim
IPC: H01L29/788 , H01L27/115
CPC classification number: H01L21/28 , H01L27/11519 , H01L27/11551 , H01L27/11553 , H01L27/11556 , H01L27/11582 , H01L29/42324 , H01L29/42364 , H01L29/66666 , H01L29/66825 , H01L29/7827 , H01L29/7841 , H01L29/788 , H01L29/7883 , H01L29/7889
Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.
Abstract translation: 提供三维非易失性存储器件及其制造方法。 存储器件包括穿透层间绝缘层的半导体柱和交替层叠在衬底上并电连接到衬底的导电层和选择性地插入在半导体柱和导电层之间的浮置栅。 浮动栅极形成在导电层中的凹部中。
-
114.发明申请THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES INCLUDING INTERPOSED FLOATING GATES 审中-公开三维非易失性存储器件，包括插入的浮动门公开(公告)号：US20140138756A1
公开(公告)日：2014-05-22
申请号：US14164408
申请日：2014-01-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byoungkeun Son , Hansoo Kim , Jinho Kim , Kihyun Kim
IPC: H01L29/788
CPC classification number: H01L21/28 , H01L27/11519 , H01L27/11551 , H01L27/11553 , H01L27/11556 , H01L27/11582 , H01L29/42324 , H01L29/42364 , H01L29/66666 , H01L29/66825 , H01L29/7827 , H01L29/7841 , H01L29/788 , H01L29/7883 , H01L29/7889
Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.
Abstract translation: 提供三维非易失性存储器件及其制造方法。 存储器件包括穿透层间绝缘层的半导体柱和交替层叠在衬底上并电连接到衬底的导电层和选择性地插入在半导体柱和导电层之间的浮置栅。 浮动栅极形成在导电层中的凹部中。
-
公开(公告)号：US08728893B2
公开(公告)日：2014-05-20
申请号：US13775453
申请日：2013-02-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byoungkeun Son , Jinho Kim , Hansoo Kim , Wonjun Lee , Daehyun Jang
IPC: H01L21/336
CPC classification number: H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/42336 , H01L29/42352 , H01L29/4236 , H01L29/66666 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7889 , H01L29/7926
Abstract: A method of fabricating a semiconductor memory device includes alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate, forming an active pattern penetrating the sacrificial layers and the insulating layers, continuously patterning the insulating layers and the sacrificial layers to form a trench, removing the sacrificial layers exposed in the trench to form recess regions exposing a sidewall of the active pattern, forming an information storage layer on the substrate, forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer, and performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other.
Abstract translation: 一种制造半导体存储器件的方法包括在衬底上交替地和重复堆叠牺牲层和绝缘层，形成穿透牺牲层和绝缘层的有源图案，连续地图案化绝缘层和牺牲层以形成沟槽，去除 所述牺牲层暴露在所述沟槽中以形成暴露所述有源图案的侧壁的凹陷区域，在所述衬底上形成信息存储层，在所述信息存储层上形成栅极导电层，使得所述栅极导电层填充所述凹部区域， 在沟槽中限定空区域，空区域被栅极导电层包围，并且相对于栅极导电层执行各向同性蚀刻处理，以在凹陷区域中形成栅电极，使得栅电极与每个栅电极分离 其他。
-
Patent Agency Ranking
公开(公告)号：US12225362B2
公开(公告)日：2025-02-11
申请号：US17695254
申请日：2022-03-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyusang Ryu , Jinho Kim , Hongbum Park , Gwanyeol Lee , Sungjun Choi , Sungpill Hwang , Doosuk Kang
IPC: H04R3/12 , G06F3/16 , H04M1/72412
Abstract: An electronic device for transmitting audio data to a plurality of external electronic devices, and a method for controlling same are provided. The electronic device includes an audio module, a communication module, and a processor. The processor can control the communication module to identify connections between the electronic device and the plurality of external electronic devices, identify properties of each of the plurality of external electronic devices connected to the electronic device, and control the audio module and the communication module so as to transmit audio data having a designated volume level to each of the plurality of external electronic devices according to the identified properties of the plurality of external electronic devices.
-
公开(公告)号：US12216167B2
公开(公告)日：2025-02-04
申请号：US17510670
申请日：2021-10-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ju Wan Lim , Daeryong Jung , Jinho Kim , Young Hun Sung , Duk Jin Oh , Myeongjae Lee
IPC: G01R31/367 , G01R31/3828 , H02J7/00
Abstract: To generate a charging path for a battery, a method includes generating simulation data for charging currents based on a battery model indicating an internal state of a battery, generating an initial look-up table (LUT) for the charging currents and preset battery voltage limits based on the simulation data, the initial LUT representing initial charging limit conditions of the battery for stages corresponding to the charging currents, generating a modified LUT by adjusting at least one of the initial charging limit conditions of the initial LUT, in response to the initial LUT failing to satisfy a threshold, determining a final LUT based on the modified LUT, in response to the modified LUT satisfying the threshold, and generating a charging path for the battery based on the final LUT.
-
公开(公告)号：US12198611B2
公开(公告)日：2025-01-14
申请号：US18129504
申请日：2023-03-31
Inventor： Jinho Kim , Yong-Sang Kim , Donggun Oh , Jongsu Oh , Eun Kyo Jung
Abstract: In a display apparatus, a display panel includes a pixel array of pixels, each pixel disposed on one of a plurality of row lines and including a plurality of inorganic LEDs, and a sub pixel circuit corresponding to each of the plurality of LEDs. Each sub pixel circuit includes a PMOSFET driving transistor, and drives a corresponding LED based on an applied image data voltage. A sensing part senses a current through the driving transistor of at least one sub pixel circuit based on a specified voltage applied to the sub pixel circuit, and outputs corresponding sensing data. A correcting part corrects an image data voltage applied to the sub pixel circuit based on the sensing data. In each LED, an anode electrode is coupled to a common node to which a driving voltage is applied, and a cathode electrode is coupled to a source terminal of the driving transistor.
-
公开(公告)号：US20250016038A1
公开(公告)日：2025-01-09
申请号：US18889979
申请日：2024-09-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinho Kim , Jungmin Park
Abstract: A user terminal supporting carrier aggregation (CA) and an operating method thereof are provided. The operating method includes receiving indication information regarding a phase tracking reference signal (PTRS) component carrier (CC) group from a base station; determining whether a phase noise characteristic of the user terminal is the same with respect to CCs included in the PTRS CC group, based at least in part on the indication information; requesting the base station to transmit at least one PTRS using at least one CC included in the PTRS CC group; and receiving the at least one PTRS from the base station using the at least one CC.
-
公开(公告)号：US12144040B2
公开(公告)日：2024-11-12
申请号：US17530093
申请日：2021-11-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinho Kim , Minji Kim , Jaejun Sim , Geunyoung Yu , Minju Lee
Abstract: Provided is an electronic device including a Wi-Fi module and a processor. The Wi-Fi module includes circuitry including a first communication interface operating as a Wi-Fi station and configured to perform communication, and a second communication interface configured to perform communication based on Wi-Fi Direct. The processor is configured to execute at least one instruction. The processor is configured to: control the Wi-Fi module to set an operation mode of the second communication interface to a first mode for performing communication by operating as the Wi-Fi station, and perform communication connection with a second access point (AP) via the second communication interface in the first mode while connection with a first AP is maintained through the first communication interface.
-
-
-
-
-
-
-
-
-
Search Results
155
records
(took 0.022 seconds)
