公开(公告)号：US20210408038A1

公开(公告)日：2021-12-30

申请号：US17231523

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Feng-Cheng Yang ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H01L27/11582 ,  G11C8/14 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.

公开(公告)号：US20210407980A1

公开(公告)日：2021-12-30

申请号：US17138270

申请日：2020-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Yu-Ming Lin

IPC: H01L25/18 ,  H01L29/24 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L27/1159 ,  H01L27/11597 ,  H01L23/48

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die is bonded to the being structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

公开(公告)号：US20210398992A1

公开(公告)日：2021-12-23

申请号：US17132305

申请日：2020-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H01L27/11502 ,  G11C5/06 ,  G11C11/22 ,  H01L27/11585

Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.

公开(公告)号：US20210375932A1

公开(公告)日：2021-12-02

申请号：US17113249

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chen Wang ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.

公开(公告)号：US20210375929A1

公开(公告)日：2021-12-02

申请号：US17070536

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

公开(公告)号：US20210273113A1

公开(公告)日：2021-09-02

申请号：US16939909

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Han-Jong Chia ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51

Abstract: A method includes providing a structure having a substrate, gate stacks and source/drain (S/D) features over the substrate, S/D contacts over the S/D features, one or more dielectric layers over the gate stacks and the S/D contacts, and a via structure penetrating the one or more dielectric layers and electrically connecting to one of the gate stacks and the S/D contacts. The method further includes forming a ferroelectric (FE) stack over the structure, wherein the FE stack includes an FE layer and a top electrode layer over the FE layer, wherein the FE stack directly contacts the via structure; and patterning the FE stack, resulting in a patterned FE stack including a patterned FE feature and a patterned top electrode over the patterned FE feature.

公开(公告)号：US11087843B1

公开(公告)日：2021-08-10

申请号：US16785997

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: G11C14/00 ,  G11C11/22 ,  H01L27/1159 ,  H01L27/11507 ,  H01L27/11 ,  G11C11/419

Abstract: Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, and a plurality of static random access memory (SRAM) cells arranged in a second memory array. There are more FRAM cells than SRAM cells. The first memory array and the second memory array share the same bus.

公开(公告)号：US20210184043A1

公开(公告)日：2021-06-17

申请号：US16868675

申请日：2020-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  G11C11/22

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a ferroelectric structure overlying a substrate. A pair of source/drain regions are disposed in the substrate. A gate dielectric layer overlies the substrate and is spaced laterally between the pair of source/drain regions. The ferroelectric structure overlies the gate dielectric layer. The ferroelectric structure includes a ferroelectric layer and a sidewall spacer structure, where the sidewall spacer structure continuously laterally wraps around the ferroelectric layer. The ferroelectric layer comprises a first metal oxide and the sidewall spacer structure comprises a second metal oxide different than the first metal oxide.