公开(公告)号：US20220384619A1

公开(公告)日：2022-12-01

申请号：US17881866

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Lo-Heng Chang ,  Jung-Hung Chang ,  Kuo-Cheng Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423

Abstract: Semiconductor devices using a dielectric structure and methods of manufacturing are described herein. The semiconductor devices are directed towards gate-all-around (GAA) devices that are formed over a substrate and are isolated from one another by the dielectric structure. The dielectric structure is formed over the fin between two GAA devices and cuts a gate electrode that is formed over the fin into two separate gate electrodes. The two GAA devices are also formed with bottom spacers underlying source/drain regions of the GAA devices. The bottom spacers isolate the source/drain regions from the substrate. The dielectric structure is formed with a shallow bottom that is located above the bottoms of the bottom spacers.

公开(公告)号：US20220367463A1

公开(公告)日：2022-11-17

申请号：US17874478

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hung Chang ,  Lo-Heng Chang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US11469326B2

公开(公告)日：2022-10-11

申请号：US17025903

申请日：2020-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Cheng Chen ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien-Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

Abstract: Embodiments of the present disclosure relate to an un-doped or low-doped epitaxial layer formed below the source/drain features. The un-doped or low-doped epitaxial layer protects the source/drain features from damage during replacement gate processes, and also prevent leakage currents in the mesa device. A semiconductor device is disclosed. The semiconductor device includes an epitaxial feature having a dopant of a first concentration, and a source/drain feature in contact with the epitaxial feature. The source/drain feature comprises the dopant of a second concentration, and the second concentration is higher than the first concentration.

公开(公告)号：US20220246614A1

公开(公告)日：2022-08-04

申请号：US17728247

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien Huang ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Shi Ning Ju ,  Guan-Lin Chen

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

公开(公告)号：US11245036B1

公开(公告)日：2022-02-08

申请号：US16935000

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.

公开(公告)号：US20210351079A1

公开(公告)日：2021-11-11

申请号：US17068037

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Zhi-Chang Lin ,  Li-Zhen Yu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor transistor device. The method comprises forming a fin-shaped channel structure over a substrate and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure. The method further comprises forming a metal gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

公开(公告)号：US11152487B2

公开(公告)日：2021-10-19

申请号：US16532107

申请日：2019-08-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh Su ,  Zhi-Chang Lin ,  Ting-Hung Hsu ,  Jia-Ni Yu ,  Wei-Hao Wu ,  Chih-Hao Wang

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L29/165

Abstract: A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes forming a gate electrode layer in a gate trench; filling a recess in the gate electrode layer with a dielectric feature; and etching back the gate electrode layer from top end surfaces of the gate electrode layer while leaving a portion of the gate electrode layer under the dielectric feature.

公开(公告)号：US20210296313A1

公开(公告)日：2021-09-23

申请号：US17131542

申请日：2020-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Chih-Hao Wang ,  Kuo-Cheng Ching

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/66 ,  H01L29/78

Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

公开(公告)号：US20210280694A1

公开(公告)日：2021-09-09

申请号：US17322267

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US11114566B2

公开(公告)日：2021-09-07

申请号：US16033256

申请日：2018-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang Lin ,  Kai-Chieh Yang ,  Chia-Wei Su ,  Jia-Ni Yu ,  Wei-Hao Wu ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/302 ,  H01L23/532 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.