公开(公告)号：US11205475B2

公开(公告)日：2021-12-21

申请号：US16870211

申请日：2020-05-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Yu Lin ,  Wei-Cheng Wu ,  Kao-Cheng Lin ,  Yen-Huei Chen

IPC分类号： G11C11/419

摘要： A static random access memory (SRAM) includes a first memory cell array, a second memory cell array, a first data line coupled to the first memory cell array and the second memory cell array, a second data line coupled to the first memory cell array and the second memory cell array, a primary driver circuit coupled to at least the first data line, and a supplementary driver circuit coupled to at least the first data line. The supplementary driver circuit is configured to receive a supplementary driver circuit enable signal, sense a voltage of a first signal of the first data line, and pull the voltage of the first signal to a first voltage level during a write operation of the SRAM in response to at least a first NOR output signal.

公开(公告)号：US20210287740A1

公开(公告)日：2021-09-16

申请号：US17334083

申请日：2021-05-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng Wu ,  Hung-Jen Liao ,  Ping-Wei Wang ,  Wei Min Chan ,  Yen-Huei Chen

IPC分类号： G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/41 ,  G11C11/412

摘要： A static random access memory (SRAM) includes a bit cell including a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a read multiplexer connected to the bit information path. The read multiplexer includes an n-type transistor configured to selectively couple the bit information path to a sense amplifier.

公开(公告)号：US11043264B2

公开(公告)日：2021-06-22

申请号：US16884774

申请日：2020-05-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng Wu ,  Wei Min Chan ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Ping-Wei Wang

IPC分类号： G11C11/41 ,  G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/412

摘要： A method of performing a write operation on a static random access memory (SRAM) bit cell includes activating the bit cell by supplying a signal to a p-type pass gate of the bit cell, the signal causing the p-type pass gate to be in a conductive state, using a p-type transistor of a write multiplexer to maintain a data line at a logically high voltage, and transferring bit information from the data line to the activated bit cell using the p-type pass gate.

公开(公告)号：US10650882B2

公开(公告)日：2020-05-12

申请号：US14515253

申请日：2014-10-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Yu Lin ,  Wei-Cheng Wu ,  Kao-Cheng Lin ,  Yen-Huei Chen

IPC分类号： G11C11/419

摘要： A static random access memory (SRAM) including at least a first memory cell array, a second memory cell array, a first data line connected to the first memory cell array and the second memory cell array, a primary driver circuit connected to the first data line and a supplementary driver circuit connected to the first data line, wherein the supplementary driver circuit is configured to pull a voltage level of the first data line to a first voltage level during a write operation of the SRAM.

公开(公告)号：US20200058616A1

公开(公告)日：2020-02-20

申请号：US16661636

申请日：2019-10-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L23/538

摘要： An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.

公开(公告)号：US20190341360A1

公开(公告)日：2019-11-07

申请号：US16511777

申请日：2019-07-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Hsien-Wei Chen ,  Meng-Tsan Lee ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Chien-Chia Chiu ,  Chin-Te Wang

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L21/683 ,  H01L25/10 ,  H01L25/00

摘要： A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.

公开(公告)号：USRE47709E1

公开(公告)日：2019-11-05

申请号：US15336265

申请日：2016-10-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Chun Hsieh ,  Wei-Cheng Wu ,  Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L21/283 ,  H01L23/48 ,  H01L21/74

摘要： A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.

公开(公告)号：US20190326302A1

公开(公告)日：2019-10-24

申请号：US16458970

申请日：2019-07-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yen-Huei Chen ,  Hung-Jen Liao ,  Chih-Yu Lin ,  Jonathan Tsung-Yung Chang ,  Wei-Cheng Wu

IPC分类号： H01L27/11 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532 ,  G11C11/419 ,  G11C11/412 ,  H01L23/528

摘要： A memory circuit including: a first column of memory cells, each memory cell of the first column including a first supply segment; a first supply voltage line in a first conductive layer, the first supply voltage line being made of at least the first supply segments of the first column; a second supply voltage line; a first resistive device electrically connecting the first and second supply voltage lines, and being located in a via layer; a first material, from which the first resistive device is formed, being different than a second material from which a first type of via plug in the via layer is formed; and a supply voltage source electrically coupled with first supply voltage line through one or more conductive paths, and the second supply voltage line and the first resistive device being in a lowest resistance path of the one or more conductive paths.

公开(公告)号：US10453813B2

公开(公告)日：2019-10-22

申请号：US15633414

申请日：2017-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chang-Chia Huang ,  Tsung-Shu Lin ,  Cheng-Chieh Hsieh ,  Wei-Cheng Wu

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L33/48 ,  H01L23/00 ,  H01L23/488 ,  H01L21/768 ,  H01L21/683 ,  H01L25/10

摘要： A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

公开(公告)号：US20190115299A1

公开(公告)日：2019-04-18

申请号：US16206850

申请日：2018-11-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L21/306 ,  H01L23/14 ,  H01L23/495 ,  H01L23/532 ,  H01L21/48

摘要： An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.