公开(公告)号：US20220102288A1

公开(公告)日：2022-03-31

申请号：US17033574

申请日：2020-09-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wensen Hung ,  Hsuan-Ning Shih ,  Hsien-Pin Hu ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wen-Hsin Wei

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/053 ,  H01L23/367 ,  H01L21/52

摘要： A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a cap and outer flanges. The cap overlies the semiconductor package. The outer flanges are disposed at edges of the cap, are connected with the cap, and extend towards the circuit substrate. A region of the bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package.

公开(公告)号：US10163856B2

公开(公告)日：2018-12-25

申请号：US14928844

申请日：2015-10-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Ming Chen ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Wen Hsin Wei

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

摘要： A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.

公开(公告)号：US10014252B2

公开(公告)日：2018-07-03

申请号：US15201122

申请日：2016-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Cheng Chang ,  Liang-Chen Lin ,  Fu-Tsai Hou ,  Tung-Chin Yeh ,  Shih-Kai Lin ,  Gia-Her Lu ,  Jyun-Lin Wu ,  Hsien-Pin Hu

IPC分类号： H01L23/525 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L23/5256 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

公开(公告)号：US09589857B2

公开(公告)日：2017-03-07

申请号：US14846605

申请日：2015-09-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzuan-Horng Liu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L21/66 ,  G01R1/073 ,  H01L23/498 ,  H01L23/522 ,  H01L23/58 ,  H01L21/56 ,  H01L21/683

CPC分类号： H01L22/32 ,  G01R1/07378 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/6835 ,  H01L22/30 ,  H01L22/34 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/585 ,  H01L2221/68331 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05124 ,  H01L2224/05147

摘要： An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

摘要翻译： 本公开的实施例是包括插入器的结构。 插入器具有沿着插入件的周边延伸的测试结构，并且测试结构的至少一部分处于第一再分配元件中。 第一再分配元件位于中介层的衬底的第一表面上。 测试结构是中间的并且电耦合到至少两个探针焊盘。

公开(公告)号：US09373673B2

公开(公告)日：2016-06-21

申请号：US14719115

申请日：2015-05-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiao-Tsung Yen ,  Chin-Wei Kuo ,  Hsien-Pin Hu ,  Sally Liu ,  Ming-Fa Chen ,  Jhe-Ching Lu

IPC分类号： H01L49/02 ,  H01F17/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01F27/28 ,  H01L21/283 ,  H01L23/00

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F27/2804 ,  H01L21/283 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

摘要： In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

公开(公告)号：US20150102482A1

公开(公告)日：2015-04-16

申请号：US14052365

申请日：2013-10-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzuan-Horng Liu ,  Shih-Wen Huang ,  Chung-Yu Lu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76805 ,  H01L21/486 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/97 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

摘要： Various embodiments of mechanisms for forming through a three-dimensional integrated circuit (3DIC) structure are provided. The 3DIC structure includes an interposer bonded to a die and a substrate. The interposer has a conductive structure with through silicon vias (TSVs) connected to a patterned metal pad and a conductive structure on opposite ends of the TSVs. The pattern metal pad is embedded with dielectric structures to reduce dishing effect and has regions over TSVs that are free of the dielectric structures. The conductive structure has 2 or more TSVs. By using a patterned metal pad and 2 or more TSVs, the reliability and yield of the conductive structure and the 3DIC structure are improved.

摘要翻译： 提供了通过三维集成电路（3DIC）结构形成机构的各种实施例。 3DIC结构包括结合到管芯和衬底的插入器。 插入器具有通过硅通孔（TSV）连接到图案化金属焊盘的导电结构和在TSV的相对端上的导电结构。 图形金属焊盘嵌入电介质结构以减少凹陷效应，并且具有不含电介质结构的TSV上的区域。 导电结构具有2个以上的TSV。 通过使用图案化的金属焊盘和2个以上的TSV，提高了导电结构和3DIC结构的可靠性和产量。

公开(公告)号：US20220359476A1

公开(公告)日：2022-11-10

申请号：US17870850

申请日：2022-07-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Pin Hu ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu ,  Wen-Hsin Wei ,  Chih-Chien Pan

IPC分类号： H01L25/16 ,  H01L23/498 ,  H01L21/56 ,  H01L23/053 ,  H01L23/10 ,  H01L23/16

摘要： A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material.

公开(公告)号：US20200219786A1

公开(公告)日：2020-07-09

申请号：US16371769

申请日：2019-04-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wensen Hung ,  Tsung-Yu Chen ,  Tsung-Shu Lin ,  Chen-Hsiang Lao ,  Wen-Hsin Wei ,  Hsien-Pin Hu

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/40 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/67

摘要： A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.

公开(公告)号：US10665474B2

公开(公告)日：2020-05-26

申请号：US16362012

申请日：2019-03-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Wei Chiu ,  Cheng-Hsien Hsieh ,  Hsien-Pin Hu ,  Kuo-Ching Hsu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56

摘要： Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

公开(公告)号：US20200152602A1

公开(公告)日：2020-05-14

申请号：US16740975

申请日：2020-01-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Hsin Wei ,  Hsien-Pin Hu ,  Shang-Yun Hou

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/18

摘要： Structures and formation methods of a chip package are provided. The chip package includes a substrate, a first chip stack attached to the substrate, and a second chip stack attached to the substrate. The first chip stack and the second chip stack being attached to a same side of the substrate. The chip package further includes a molding compound layer surrounding the first chip stack and the second chip stack. The molding compound layer covers a topmost surface of the first chip stack. A topmost surface of the molding compound layer is substantially coplanar with a topmost surface of the second chip stack.