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公开(公告)号：US11955439B2
公开(公告)日：2024-04-09
申请号：US18155672
申请日：2023-01-17
发明人： Wei-Cheng Wu , Chien-Chia Chiu , Cheng-Hsien Hsieh , Li-Han Hsu , Meng-Tsan Lee , Tsung-Shu Lin
IPC分类号： H01L23/552 , H01L21/56 , H01L21/76 , H01L21/768 , H01L23/00 , H01L23/31 , H01L23/488 , H01L23/538
CPC分类号： H01L23/552 , H01L21/56 , H01L21/76802 , H01L21/76877 , H01L23/31 , H01L23/488 , H01L23/5384 , H01L24/14
摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
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公开(公告)号：US11756870B2
公开(公告)日：2023-09-12
申请号：US17243600
申请日：2021-04-29
发明人： Che-Yu Yeh , Tsung-Shu Lin , Wei-Cheng Wu , Tsung-Yu Chen , Li-Han Hsu , Chien-Fu Tseng
IPC分类号： H01L23/498 , H01L23/48 , H01L25/065 , H01L23/00
CPC分类号： H01L23/49822 , H01L23/481 , H01L23/49816 , H01L23/49838 , H01L24/20 , H01L24/24 , H01L25/0652 , H01L2224/2101 , H01L2224/214 , H01L2224/2105 , H01L2224/24226 , H01L2924/182
摘要： A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
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公开(公告)号：US20200083156A1
公开(公告)日：2020-03-12
申请号：US16685645
申请日：2019-11-15
发明人： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Li-Han Hsu , Wei-Cheng Wu
IPC分类号： H01L23/498 , H01L23/58 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/31
摘要： A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
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公开(公告)号：US20190295955A1
公开(公告)日：2019-09-26
申请号：US16436494
申请日：2019-06-10
发明人： Cheng-Hsien Hsieh , Li-Han Hsu , Wei-Cheng Wu , Hsien-Wei Chen , Der-Chyang Yeh , Chi-Hsi Wu , Chen-Hua Yu
摘要： An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
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公开(公告)号：US20190098756A1
公开(公告)日：2019-03-28
申请号：US16203919
申请日：2018-11-29
发明人： Cheng-Hsien Hsieh , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Hsien-Wei Chen , Li-Han Hsu , Wei-Cheng Wu
摘要： A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
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公开(公告)号：US10165682B2
公开(公告)日：2018-12-25
申请号：US14979954
申请日：2015-12-28
发明人： Cheng-Hsien Hsieh , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Hsien-Wei Chen , Li-Han Hsu , Wei-Cheng Wu
摘要： A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
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公开(公告)号：US09754831B2
公开(公告)日：2017-09-05
申请号：US15243527
申请日：2016-08-22
发明人： Pei-Ching Kuo , Yi-Hsiu Chen , Jun-Lin Yeh , Yung-Chi Lin , Li-Han Hsu , Wei-Cheng Wu , Ku-Feng Yang , Wen-Chih Chiou
IPC分类号： H01L21/768 , H01L23/48 , H01L23/00 , H01L23/528 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76898 , H01L21/76802 , H01L21/7684 , H01L21/76879 , H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L24/06 , H01L2224/05025 , H01L2924/2075 , H01L2924/20751
摘要： Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
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公开(公告)号：US20170133282A1
公开(公告)日：2017-05-11
申请号：US15414909
申请日：2017-01-25
发明人： Wei-Cheng Wu , Li-Han Hsu , Sao-Ling Chiu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Lin
IPC分类号： H01L21/66 , G01R1/073 , H01L25/065 , H01L25/00 , H01L23/00 , G01R31/28 , G01R31/265
CPC分类号： H01L22/14 , G01R1/07314 , G01R31/265 , G01R31/2884 , H01L22/12 , H01L22/32 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/16055 , H01L2224/16113 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/1713 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596
摘要： An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.
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9.发明申请Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages 有权芯片上晶片上基片封装上的晶片过渡控制监控公开(公告)号：US20140266283A1
公开(公告)日：2014-09-18
申请号：US13905958
申请日：2013-05-30
发明人： Wei-Cheng Wu , Li-Han Hsu , Sao-Ling Chiu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Lin
IPC分类号： G01R31/26
CPC分类号： H01L22/14 , G01R1/07314 , G01R31/265 , G01R31/2884 , H01L22/12 , H01L22/32 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/16055 , H01L2224/16113 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/1713 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596
摘要： An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.
摘要翻译： 一种实施方式包括提供晶片芯片（CoW）结构的标准化测试结构设计，其中标准化测试结构设计包括将测试结构放置在CoW结构中的顶部模具的预选区域内，并且电测试 通过在测试结构上应用通用测试探针卡，在CoW结构中的多个微胶片。
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公开(公告)号：US11018088B2
公开(公告)日：2021-05-25
申请号：US16436494
申请日：2019-06-10
发明人： Cheng-Hsien Hsieh , Li-Han Hsu , Wei-Cheng Wu , Hsien-Wei Chen , Der-Chyang Yeh , Chi-Hsi Wu , Chen-Hua Yu
摘要： An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
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