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    Memory device
    2.
    发明授权
    Memory device 有权

    公开(公告)号：US12165731B2

    公开(公告)日：2024-12-10

    申请号：US18447910

    申请日：2023-08-10

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chien-Chen Lin ,  Wei Min Chan

    IPC: G11C16/10 ,  G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08

    Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

    Memory Device
    7.
    发明公开
    Memory Device 审中-公开

    公开(公告)号：US20240161787A1

    公开(公告)日：2024-05-16

    申请号：US18447910

    申请日：2023-08-10

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chien-Chen Lin ,  Wei Min Chan

    IPC: G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08

    CPC classification number: G11C5/148 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08

    Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

    Static random access memory (SRAM) with recovery circuit for a write operation
    8.
    发明授权
    Static random access memory (SRAM) with recovery circuit for a write operation 有权

    公开(公告)号：US09799394B2

    公开(公告)日：2017-10-24

    申请号：US14696795

    申请日：2015-04-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Wei-Cheng Wu ,  Kao-Cheng Lin ,  Wei Min Chan ,  Yen-Huei Chen

    IPC: G11C11/419

    CPC classification number: G11C11/419

    Abstract: A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The first data line is electrically coupled with the memory cell array. The second data line is electrically coupled with the memory cell array. The driver circuit is electrically coupled with the first data line, the second data line and the third data line. The driver circuit includes a recovery circuit electrically coupled with the first data line, the second data line and the third data line. During a write operation of the SRAM, the recovery circuit is configured to pull a voltage level of the first data line to a first voltage level when the recovery circuit is enabled.

    Static random access memory with assist circuit
    10.
    发明授权
    Static random access memory with assist circuit 有权
    具有辅助电路的静态随机存取存储器

    公开(公告)号：US09208858B1

    公开(公告)日：2015-12-08

    申请号：US14331799

    申请日：2014-07-15

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Kao-Cheng Lin ,  Hidehiro Fujiwara ,  Wei Min Chan ,  Yen-Huei Chen

    IPC: G11C8/00 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412

    Abstract: A static random access memory (SRAM) includes a first port word line, a second port word line, a first port bit line and a first port complementary bit line, a second port bit line and second port complementary bit line, and a memory cell having a data node coupled to the first and second port bit lines and a complementary data node coupled to the first and second port complementary bit lines. The first and second port word lines control access to the dual port memory cell. A circuit couples the second port bit line to a high voltage supply node during a write logic high operation to the data node through the first port bit line and couple the second port complementary bit line to the high voltage supply node during a write logic high operation to the complementary data node through the first port complementary bit line.

    Abstract translation: 静态随机存取存储器（SRAM）包括第一端口字线，第二端口字线，第一端口位线和第一端口互补位线，第二端口位线和第二端口互补位线，以及存储器单元 具有耦合到第一和第二端口位线的数据节点和耦合到第一和第二端口互补位线的互补数据节点。 第一和第二端口字线控制对双端口存储单元的访问。 在写入逻辑高操作期间，电路通过第一端口位线将第二端口位线耦合到高电压电源节点到数据节点，并且在写入逻辑高操作期间将第二端口互补位线耦合到高电压电源节点 通过第一个端口互补位线到互补数据节点。

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