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公开(公告)号：US11955439B2
公开(公告)日：2024-04-09
申请号：US18155672
申请日：2023-01-17
发明人： Wei-Cheng Wu , Chien-Chia Chiu , Cheng-Hsien Hsieh , Li-Han Hsu , Meng-Tsan Lee , Tsung-Shu Lin
IPC分类号： H01L23/552 , H01L21/56 , H01L21/76 , H01L21/768 , H01L23/00 , H01L23/31 , H01L23/488 , H01L23/538
CPC分类号： H01L23/552 , H01L21/56 , H01L21/76802 , H01L21/76877 , H01L23/31 , H01L23/488 , H01L23/5384 , H01L24/14
摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
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公开(公告)号：US11069539B2
公开(公告)日：2021-07-20
申请号：US16863518
申请日：2020-04-30
发明人： Tzu-Wei Chiu , Cheng-Hsien Hsieh , Hsien-Pin Hu , Kuo-Ching Hsu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号： H01L21/48 , H01L23/498 , H01L21/683 , H01L21/56
摘要： Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.
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公开(公告)号：US20200083156A1
公开(公告)日：2020-03-12
申请号：US16685645
申请日：2019-11-15
发明人： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Li-Han Hsu , Wei-Cheng Wu
IPC分类号： H01L23/498 , H01L23/58 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/31
摘要： A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
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公开(公告)号：US20190295955A1
公开(公告)日：2019-09-26
申请号：US16436494
申请日：2019-06-10
发明人： Cheng-Hsien Hsieh , Li-Han Hsu , Wei-Cheng Wu , Hsien-Wei Chen , Der-Chyang Yeh , Chi-Hsi Wu , Chen-Hua Yu
摘要： An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
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公开(公告)号：US20190252334A1
公开(公告)日：2019-08-15
申请号：US16390814
申请日：2019-04-22
发明人： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chen-Hua Yu , Tsung-Shu Lin , Wei-Cheng Wu
CPC分类号： H01L24/05 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/481 , H01L23/562 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/19 , H01L25/105 , H01L25/50 , H01L2224/0231 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/35121 , H01L2924/00012 , H01L2924/00
摘要： A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.
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公开(公告)号：US10276532B2
公开(公告)日：2019-04-30
申请号：US15640997
申请日：2017-07-03
IPC分类号： H01L23/00 , B23K1/00 , H01L25/065 , H01L25/00 , H01L23/538 , B23K101/40
摘要： A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.
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公开(公告)号：US20190098756A1
公开(公告)日：2019-03-28
申请号：US16203919
申请日：2018-11-29
发明人： Cheng-Hsien Hsieh , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Hsien-Wei Chen , Li-Han Hsu , Wei-Cheng Wu
摘要： A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
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公开(公告)号：US10165682B2
公开(公告)日：2018-12-25
申请号：US14979954
申请日：2015-12-28
发明人： Cheng-Hsien Hsieh , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Hsien-Wei Chen , Li-Han Hsu , Wei-Cheng Wu
摘要： A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
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公开(公告)号：US20170005052A1
公开(公告)日：2017-01-05
申请号：US14788182
申请日：2015-06-30
发明人： Wei-Yu Chen , Hsien-Wei Chen , An-Jhih Su , Cheng-Hsien Hsieh
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L21/76885 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/02245 , H01L2224/02251 , H01L2224/02255 , H01L2224/0231 , H01L2224/02379 , H01L2224/024 , H01L2224/03462 , H01L2224/03464 , H01L2224/03472 , H01L2224/03622 , H01L2224/03828 , H01L2224/0391 , H01L2224/0401 , H01L2224/04105 , H01L2224/05012 , H01L2224/05015 , H01L2224/05022 , H01L2224/05024 , H01L2224/05027 , H01L2224/05548 , H01L2224/05555 , H01L2224/05572 , H01L2224/05575 , H01L2224/11334 , H01L2224/12105 , H01L2224/13014 , H01L2224/13016 , H01L2224/13022 , H01L2224/131 , H01L2224/73267 , H01L2924/2064 , H01L2924/00014 , H01L2924/00012 , H01L2924/014
摘要： A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die.
摘要翻译： 器件封装包括管芯上的管芯，扇出的再分布层（RDL）以及在扇出RDL上的凸起下冶金（UBM）。 UBM包括导电焊盘部分和环绕导电焊盘部分的沟槽。 器件封装还包括设置在UBM的导电焊盘部分上的连接器。 扇出式RDL将连接器和UBM电连接到管芯。
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公开(公告)号：US20160181124A1
公开(公告)日：2016-06-23
申请号：US15054770
申请日：2016-02-26
发明人： Tzu-Wei Chiu , Cheng-Hsien Hsieh , Hsien-Pin Hu , Kuo-Ching Hsu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号： H01L21/48
CPC分类号： H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L21/6835 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49894 , H01L2221/68318 , H01L2221/68345 , H01L2221/68381 , H01L2224/13 , H01L2224/73204
摘要： Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.
摘要翻译： 本公开的实施例包括半导体器件和形成半导体器件的方法。 一个实施例是一种半导体器件，包括由多个薄膜层和设置在其中的多个金属层组成的互连结构，多个金属层中的每一个具有基本上相同的顶表面积，以及模具，其包括活性表面和 与所述有源表面相对的背面，所述有源表面直接耦合到所述互连结构的第一侧。 半导体器件还包括直接耦合到互连结构的第二侧的第一连接器，第二侧与第一侧相对。
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