公开(公告)号：US12063792B2

公开(公告)日：2024-08-13

申请号：US18207654

申请日：2023-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen ,  Wei Chen

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.

公开(公告)号：US12052931B2

公开(公告)日：2024-07-30

申请号：US18079890

申请日：2022-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor device includes a storage element on a substrate. The storage element has a tapered upper end structure. The tapered upper end structure includes a top electrode and a spacer surrounding the top electrode. A gap-fill dielectric layer is disposed around the spacer. A conductive cap layer covers the top electrode and the spacer. An inter-metal dielectric (IMD) layer is disposed on the conductive cap layer. A metal interconnection is disposed in the IMD layer and electrically connected to the top electrode through the conductive cap layer.

公开(公告)号：US12029139B2

公开(公告)日：2024-07-02

申请号：US18202275

申请日：2023-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Si-Han Tsai ,  Che-Wei Chang ,  Jing-Yin Jhang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

公开(公告)号：US20240196756A1

公开(公告)日：2024-06-13

申请号：US18587823

申请日：2024-02-26

Applicant: United Microelectronics Corp.

Inventor： Hui-Lin Wang ,  Wei Chen ,  Po-Kai Hsu ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10N50/01 ,  H01F10/32 ,  H10N50/80

CPC classification number: H10N50/01 ,  H01F10/3254 ,  H01F10/329 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

公开(公告)号：US20240172456A1

公开(公告)日：2024-05-23

申请号：US18420684

申请日：2024-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hui-Lin Wang ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Ju-Chun Fan ,  Hung-Yueh Chen

IPC: H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N70/063 ,  H10N70/24 ,  H10N70/826 ,  H10N70/8833

Abstract: A method of manufacturing a hybrid random access memory in a system-on-chip, including steps of providing a semiconductor substrate with a magnetoresistive random access memory (MRAM) region and a resistive random-access memory (ReRAM) region, forming multiple ReRAM cells in the ReRAM region on the semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, wherein the ReRAM cells are in the first dielectric layer, forming multiple MRAM cells in the MRAM region on the first dielectric layer, and forming a second dielectric layer on the first dielectric layer, wherein the MRAM cells are in the second dielectric layer.

公开(公告)号：US20240130246A1

公开(公告)日：2024-04-18

申请号：US18395646

申请日：2023-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

公开(公告)号：US11957064B2

公开(公告)日：2024-04-09

申请号：US17967904

申请日：2022-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H10N50/80 ,  G11C5/06 ,  G11C11/16 ,  H01L29/82 ,  H10N50/01 ,  H10N50/10 ,  H10B61/00

CPC classification number: H10N50/80 ,  G11C5/06 ,  G11C11/16 ,  G11C11/161 ,  H01L29/82 ,  H10N50/01 ,  H10N50/10 ,  G11C2211/5615 ,  H10B61/00

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

公开(公告)号：US20240081157A1

公开(公告)日：2024-03-07

申请号：US18502103

申请日：2023-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H10N50/80 ,  G11C5/06 ,  G11C11/16 ,  H01L29/82 ,  H10N50/01 ,  H10N50/10

CPC classification number: H10N50/80 ,  G11C5/06 ,  G11C11/16 ,  G11C11/161 ,  H01L29/82 ,  H10N50/01 ,  H10N50/10 ,  G11C2211/5615 ,  H10B61/00

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

公开(公告)号：US11925035B2

公开(公告)日：2024-03-05

申请号：US17973557

申请日：2022-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hui-Lin Wang ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Ju-Chun Fan ,  Hung-Yueh Chen

IPC: H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N70/063 ,  H10N70/24 ,  H10N70/826 ,  H10N70/8833

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

公开(公告)号：US20240027549A1

公开(公告)日：2024-01-25

申请号：US18376451

申请日：2023-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Che-Wei Chang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: G01R33/09 ,  G11C11/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G01R33/093 ,  G01R33/098 ,  G11C11/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.