公开(公告)号：US5404053A

公开(公告)日：1995-04-04

申请号：US75056

申请日：1993-06-09

申请人： Alberto Poma ,  Vanni Poletto ,  Marco Morelli

发明人： Alberto Poma ,  Vanni Poletto ,  Marco Morelli

IPC分类号： H01L27/06 ,  H03F1/52 ,  H03K17/06 ,  H03K17/082 ,  H03K17/60 ,  H03K3/26

CPC分类号： H03K17/0822 ,  H03F1/523 ,  H03K17/063

摘要： An improved circuit for controlling the maximum current in a MOS power transistor, in which resistor is in series with the drain-source path of the MOS power transistor. The supply terminal of a transconductance operational amplifier is connected to the output of a voltage-raising or charge pump circuit which can output a voltage higher than that of the voltage supply to which the drain of the MOS transistor is connected. The inputs of the amplifier are connected to the resistor and its output is connected to the gate of the MOS transistor so that, in operation, the maximum current flowing through the power transistor is limited to a value proportional to a reference voltage.

摘要翻译： 一种用于控制MOS功率晶体管中的最大电流的改进电路，其中电阻器与MOS功率晶体管的漏极 - 源极路径串联。 跨导运算放大器的供电端子连接到升压或电荷泵电路的输出，该电压可以输出比MOS晶体管的漏极连接的电压高的电压。 放大器的输入连接到电阻器，其输出端连接到MOS晶体管的栅极，使得在工作中流过功率晶体管的最大电流被限制为与参考电压成比例的值。

公开(公告)号：US5400272A

公开(公告)日：1995-03-21

申请号：US45627

申请日：1993-04-09

申请人： Carla Golla ,  Sali M. Luigi

发明人： Carla Golla ,  Sali M. Luigi

IPC分类号： G06F7/52 ,  G06F7/523 ,  G06F17/10

CPC分类号： G06F7/5312

摘要： A diagonal propagation, digital multiplier of a kind adapted to multiply a first factor by a second factor, with the factors each being expressed as a binary number including a non-volatile memory having a plurality of cells each with one digit of a factor stored therein, a plurality of computation blocks cascade connected together, each block being also connected to a corresponding cell in the memory, computation stage in each of the blocks for performing a binary sum of the first factor plus one digit of the second factor, and memory elements in each of the blocks for storing therein the result of the calculation and making it available as a pseudo-carryover to the next block.

摘要翻译： 一种对角线传播，一种适于将第一因子乘以第二因子的数字乘法器，其中各个被表示为二进制数的因子包括具有存储在其中的因子的一位数的多个单元的多个单元的非易失性存储器 串联连接在一起的多个计算块，每个块也连接到存储器中的相应单元，每个块中的计算阶段用于执行第一因子加上第二因子的一位数的二进制和以及存储元件 在每个块中用于存储其中的计算结果并使其可用作伪携带到下一个块。

公开(公告)号：US5397745A

公开(公告)日：1995-03-14

申请号：US77375

申请日：1993-06-17

申请人： Giuseppe Ferla ,  Cesare Ronsisvalle ,  Pier E. Zani

发明人： Giuseppe Ferla ,  Cesare Ronsisvalle ,  Pier E. Zani

IPC分类号： H01L25/07 ,  H01L23/051 ,  H01L23/50 ,  H01L23/525 ,  H01L25/18 ,  H01L21/60

CPC分类号： H01L23/051 ,  H01L23/50 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/13055

摘要： Plural modular elementary semiconductor power components are respectively contained within plural semiconductor chip regions of a same semiconductor slice. A metallic layer covers a first surface of the semiconductor slice and is commonly connected to anode electrodes of the plural elementary power components. Plural space apart quadrangular metallic layer regions respectively cover the plural semiconductor chip regions on a second surface of the semiconductor slice and are respectively connected to cathode electrodes of the plural elementary power components. Plural first metallic tracks are spaced apart from and surround the respective plural metallic layer regions on the second surface of the semiconductor slice. Each respective first metallic track is connected to a control electrode of the elementary power component contained within the semiconductor chip regions surrounded by the respective first metallic track. Plural second metallic tracks extend spaced apart from and between the plural first metallic tracks to form a lattice configuration on the second surface of the semiconductor slice. Plural fuse elements, for selectively isolating defective elementary power components, are located on the second surface of the semiconductor slice and connect the first and second metallic tracks.

摘要翻译： 多个模块化基本半导体功率元件分别包含在相同半导体片的多个半导体芯片区域内。 金属层覆盖半导体片的第一表面，并且通常连接到多个基本功率元件的阳极电极。 多个隔开的四边形金属层区域分别覆盖半导体片的第二表面上的多个半导体芯片区域，并且分别连接到多个基本功率部件的阴极电极。 多个第一金属轨道与半导体片的第二表面上的相应的多个金属层区域间隔开并围绕。 每个相应的第一金属轨道连接到包含在由相应的第一金属轨道包围的半导体芯片区域内的基本功率分量的控制电极。 多个第二金属轨道与多个第一金属轨道间隔开并且在多个第一金属轨道之间延伸，以在半导体片的第二表面上形成晶格构型。 用于选择性地隔离有缺陷的基本功率元件的多个熔丝元件位于半导体片的第二表面上，并连接第一和第二金属轨道。

公开(公告)号：US5396119A

公开(公告)日：1995-03-07

申请号：US47803

申请日：1993-04-15

申请人： Guido Brasca ,  Edoardo Botti

发明人： Guido Brasca ,  Edoardo Botti

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/02 ,  H03K17/08 ,  H03K3/26

CPC分类号： H01L27/0248 ,  H01L27/0203

摘要： A device including a MOS power transistor, and a temperature sensor including a bipolar transistor integrated in the MOS transistor and having its emitter and collector connected directly to the source and gate terminals respectively of the MOS transistor. Parallel to the base-emitter junction of the bipolar transistor, there is connected a voltage source for biasing the junction to such a value that the bipolar transistor remains off at room temperature, and absorbs the maximum current supplied by a drive circuit of the MOS transistor at the maximum permissible temperature TUM. At temperature TUM, the bipolar transistor takes over control of the gate-source voltage of the MOS transistor for maintaining thermal feedback of the device at maximum temperature TUM.

摘要翻译： 一种包括MOS功率晶体管的器件和包括集成在MOS晶体管中的双极晶体管的温度传感器，其发射极和集电极分别直接连接到MOS晶体管的源极和栅极端子。 与双极型晶体管的基极 - 发射极并联，连接有用于将结的偏置电压到在双极晶体管在室温下保持截止的值，并且吸收由MOS晶体管的驱动电路提供的最大电流 在最大允许温度TUM。 在温度TUM下，双极晶体管控制MOS晶体管的栅极 - 源极电压，以保持器件的热反馈在最高温度TUM。

公开(公告)号：US5382538A

公开(公告)日：1995-01-17

申请号：US66336

申请日：1993-05-21

申请人： Raffaele Zambrano ,  Carmelo Magro

发明人： Raffaele Zambrano ,  Carmelo Magro

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66712 ,  H01L29/1095 ,  H01L29/7802 ,  Y10S148/126

摘要： The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.

摘要翻译： 该方法首先在侧面和栅极区域处实现低掺杂体区域，然后在所述低掺杂体区域内部实现高掺杂体区域并与所述栅极区域自对准。 因此获得了具有垂直电流的MOS功率晶体管，其具有与所述栅极区域自对准且具有减小的结深度的高掺杂体区域。

公开(公告)号：US5381044A

公开(公告)日：1995-01-10

申请号：US918440

申请日：1992-07-22

申请人： Michele Zisa ,  Massimiliano Belluso ,  Mario Paparo

发明人： Michele Zisa ,  Massimiliano Belluso ,  Mario Paparo

IPC分类号： H03F3/217 ,  H03K4/58 ,  H03K5/02 ,  H03K17/06 ,  H03K17/687 ,  H03K19/017

CPC分类号： H03K17/063 ,  H03K17/6877 ,  H03K19/01714

摘要： In accordance with the present invention, the above and other objects and advantages are obtained with a bootstrap circuit for a power MOS transistor in a high side configuration. Such circuit includes a first capacitor chargeable to a first voltage which is a function of the supply voltage of the power transistor. It further includes a second capacitor combined with the first capacitor so as to provide a second voltage which is higher than the first voltage and the threshold voltage of the power transistor.

摘要翻译： 根据本发明，通过高边配置的功率MOS晶体管的自举电路获得上述和其它目的和优点。 这种电路包括可充电到功率晶体管的电源电压的函数的第一电压的第一电容器。 其还包括与第一电容器组合的第二电容器，以便提供高于功率晶体管的第一电压和阈值电压的第二电压。

公开(公告)号：US5357217A

公开(公告)日：1994-10-18

申请号：US62468

申请日：1993-05-13

申请人： Gianmarco Marchesi ,  Guido Torelli

发明人： Gianmarco Marchesi ,  Guido Torelli

IPC分类号： G11C17/00 ,  H03K3/03 ,  H03K3/354 ,  H03K5/151 ,  H03L7/24 ,  H03B27/00

CPC分类号： H03K3/0315 ,  H03L7/24

摘要： A signal generator which includes two matched ring oscillators, and feedback gates which cross-couple each ring oscillator to the other. That is, in each oscillator, a first node gates a coupling transistor which connects a second node (complementary to the first node) across to drive the first node of the other oscillator.

摘要翻译： 包括两个匹配的环形振荡器的信号发生器和将每个环形振荡器交叉耦合到另一个的反馈门。 也就是说，在每个振荡器中，第一节点将连接第二节点（与第一节点互补）的耦合晶体管栅极连接以驱动另一个振荡器的第一节点。

公开(公告)号：US5352972A

公开(公告)日：1994-10-04

申请号：US861111

申请日：1992-03-31

申请人： Sergio Pernici ,  Germano Nicollini

发明人： Sergio Pernici ,  Germano Nicollini

IPC分类号： G05F3/30 ,  G11C27/02 ,  H03K5/08 ,  H03M1/34 ,  G05F3/16

CPC分类号： G11C27/026

摘要： A sampled band-gap voltage reference circuit which has quicker regeneration of the voltage reference signal after degeneration of the voltage reference signal due to additional loading. The voltage reference circuit prevents interference from the circuit source inputs to the operational amplifier by selective switching. The selective switching of the circuit allows the operational amplifier to regenerate the output voltage up to ten times quicker than prior art devices of the same size.

摘要翻译： 采样的带隙电压参考电路，由于额外的负载，在电压参考信号退化后具有更快的再生电压参考信号。 电压参考电路通过选择性开关来防止来自运算放大器的电路源输入的干扰。 电路的选择性切换允许运算放大器比现有技术相同尺寸的器件更快地再生输出电压的十倍。

公开(公告)号：US5321317A

公开(公告)日：1994-06-14

申请号：US936857

申请日：1992-08-27

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： G06F1/24 ,  H03K17/00 ,  H03K17/22 ,  G05F1/46

CPC分类号： H03K17/223 ,  H03K2217/0036

摘要： A power-on reset circuit, which may be utilized with CMOS integrated circuits, includes first and second series-connected inverters, wherein the output of the second inverter provides a reset signal. A series of switches and a biasing line having two series-connected diodes are integrally arranged with the inverters. Capacitive coupling to ground and the supply voltage is employed to prevent any static current path between supply voltage rails. The circuit provides a short duration reset signal which follows the supply voltage and is insensitive both to rebound signals on the supply voltage rails and to internal and external noise.

摘要翻译： 可以与CMOS集成电路一起使用的上电复位电路包括第一和第二串联连接的反相器，其中第二反相器的输出提供复位信号。 具有两个串联二极管的一系列开关和偏置线与逆变器一体地布置。 采用与地的电容耦合和电源电压来防止电源电压轨之间的任何静态电流路径。 该电路提供短暂的复位信号，该信号跟随电源电压，对电源电压轨上的回弹信号和内部和外部噪声都不敏感。

公开(公告)号：US5313114A

公开(公告)日：1994-05-17

申请号：US815158

申请日：1991-12-31

申请人： Vanni Poletto ,  Michelangelo Mazzucco

发明人： Vanni Poletto ,  Michelangelo Mazzucco

IPC分类号： H03K3/0233 ,  H03K5/22 ,  H03K3/01 ,  H03K17/56 ,  H03K17/60

CPC分类号： H03K3/02337

摘要： The amplitude of the hysteresis of the circuit is determined principally by the intensity of the current produced by a generator by means of a "band gap" reference voltage, an internal resistance of the circuit, and the resistances connected to the emitters of the input-stage transistors, enabling a high degree of precision to be achieved. The inputs of the circuit are defined by the bases of the input-stage transistors and therefore have high impedance. The preferred application is for forming interface circuits for sensors to be fitted in motor vehicles.

摘要翻译： 电路的滞后幅度主要由发电机通过“带隙”参考电压，电路的内部电阻和连接到输入 - 输出的发射极的电阻产生的电流的强度确定， 能够实现高精度。 电路的输入由输入级晶体管的基极限定，因此具有高阻抗。 优选的应用是形成用于安装在机动车辆中的传感器的接口电路。