公开(公告)号：US5541884A

公开(公告)日：1996-07-30

申请号：US391147

申请日：1995-02-21

申请人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

发明人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32 ,  G11C17/00

CPC分类号： G11C7/02 ,  G11C16/32 ,  G11C7/1006 ,  G11C7/22

摘要： In a nonvolatile memory comprising a data amplifying unit and an output element mutually connected by a connection line, the noise suppressing circuit comprises a network for generating a noise suppressing signal which is synchronized substantially perfectly with a signal controlling data loading from the amplifying unit to the output unit, presents a very short duration, equal to the switching time of the output unit, and freezes the amplifying unit during switching of the output unit to prevent this from altering the data stored in the amplifying unit or internal circuits of the memory. The same signal also blocks an address amplifying unit on the address bus.

摘要翻译： 在包括数据放大单元和通过连接线相互连接的输出元件的非易失性存储器中，噪声抑制电路包括用于产生噪声抑制信号的网络，该噪声抑制信号与控制从放大单元加载到 输出单元呈现相当于输出单元的切换时间的非常短的持续时间，并且在切换输出单元期间使放大单元冻结，以防止其改变存储在放大单元中的数据或存储器的内部电路。 相同的信号也阻塞地址总线上的地址放大单元。

公开(公告)号：US5321317A

公开(公告)日：1994-06-14

申请号：US936857

申请日：1992-08-27

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： G06F1/24 ,  H03K17/00 ,  H03K17/22 ,  G05F1/46

CPC分类号： H03K17/223 ,  H03K2217/0036

摘要： A power-on reset circuit, which may be utilized with CMOS integrated circuits, includes first and second series-connected inverters, wherein the output of the second inverter provides a reset signal. A series of switches and a biasing line having two series-connected diodes are integrally arranged with the inverters. Capacitive coupling to ground and the supply voltage is employed to prevent any static current path between supply voltage rails. The circuit provides a short duration reset signal which follows the supply voltage and is insensitive both to rebound signals on the supply voltage rails and to internal and external noise.

摘要翻译： 可以与CMOS集成电路一起使用的上电复位电路包括第一和第二串联连接的反相器，其中第二反相器的输出提供复位信号。 具有两个串联二极管的一系列开关和偏置线与逆变器一体地布置。 采用与地的电容耦合和电源电压来防止电源电压轨之间的任何静态电流路径。 该电路提供短暂的复位信号，该信号跟随电源电压，对电源电压轨上的回弹信号和内部和外部噪声都不敏感。

公开(公告)号：US4933827A

公开(公告)日：1990-06-12

申请号：US376267

申请日：1989-07-06

申请人： Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

发明人： Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

IPC分类号： H01L27/04 ,  G11C5/14 ,  G11C16/30 ,  H01L21/822 ,  H02M3/07

CPC分类号： G11C5/145 ,  G11C16/30 ,  H02M3/073

摘要： The regulation of the output voltage of a voltage multiplier driven by a ring oscillator, an inverter of which is substituted by a NOR gate for providing a terminal through which stopping the oscillation, is effected by controlling the oscillation frequency in function of the current delivered by the voltage multiplier by means of a transistor T1 working as a current generator connected in series with a regulating chain of series-connected diodes by biasing the gate of the transistor with a constant voltage Vref, thus imposing a reference current Iref through the transistor. The voltage signal across the transistor is fed to the input of a first inverter with a preset triggering threshold and the output signal of the inverter is fed through an amplifying and phase-regenerating stage to said terminal for stopping the oscillation of said NOR gate of the ring oscillator. When the discharge current through the regulating chain becomes greater than the imposed current Iref, across the transistor T1 a voltage signal develops which, beyond a certain threshold, determines the switching of the inverter and, through the amplifying and phase-regenerating stage, causes a stop of the oscillation which resumes only when conduction through the regulating chain stops. At steady state the oscillation frequency will result controlled so as to maintain constant the output voltage of the voltage multiplier and to limit the discharge current through the regulating chain thus limiting power consumption.

公开(公告)号：US5532972A

公开(公告)日：1996-07-02

申请号：US391920

申请日：1995-02-21

申请人： Luigi Pascucci ,  Silvia Padoan ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

发明人： Luigi Pascucci ,  Silvia Padoan ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C16/32 ,  G11C7/1006 ,  G11C7/22

摘要： A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.

摘要翻译： 电路包括产生用于异步地使读取相位的脉冲信号的部分; 产生预充电和检测可调节持续时间的信号的部分，用于控制从存储器读取数据并向输出缓冲器提供数据; 产生用于在加载到输出电路期间将输出缓冲器中的数据冻结的噪声抑制信号的部分，其持续时间恰好等于数据到存储器的输出电路的传播时间，如通过传播 输出仿真电路中的数据模拟信号; 产生负载信号的部分，其持续时间可以等于噪声抑制信号的延迟，或者在阵列呈现较慢的元素，由此可以被读取的情况下由扩展电路扩展; 以及产生电路复位信号的部分。

公开(公告)号：US5408148A

公开(公告)日：1995-04-18

申请号：US919606

申请日：1992-07-24

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： G11C11/417 ,  G11C7/06 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C7/065 ,  G11C16/28

摘要： The discriminating sensitivity of a sense amplifier and the speed of the circuit are increased by exploiting the difference of potential which develops across the output nodes of the two control circuits, employed for enabling/disabling current paths of the input network of the differential amplifier, as a virtual additional signal for the sensing differential amplifier, by employing said output potentials of the two control circuits as virtual reference potentials for the pair of input transistors of the differential amplifier during a discriminating phase of the reading cycle. Two pass-transistors driven by a control signal provide to force to ground potential the output nodes of said control circuits, thus reestablishing a correct ground reference potential of the amplifier, during the final phase of amplification and storage of the extracted datum in an output latch, as well as during the successive standby period. Alternative embodiments also include various anti-overshoot circuits.

摘要翻译： 读出放大器的鉴别灵敏度和电路速度通过利用两个控制电路的输出节点之间产生的电位差，用于使能/禁止差分放大器的输入网络的电流路径的差异作为 用于感测差分放大器的虚拟附加信号，通过在读取周期的识别阶段期间，将两个控制电路的所述输出电位用作差分放大器的一对输入晶体管的虚拟参考电位。 由控制信号驱动的两个通过晶体管提供强制接地电位的所述控制电路的输出节点，从而重新建立放大器的正确接地参考电位，在放大和放大输出锁存器中提取的数据的放大和存储的最后阶段期间 ，以及在连续的待命期间。 替代实施例还包括各种防过冲电路。

公开(公告)号：USRE36579E

公开(公告)日：2000-02-22

申请号：US488718

申请日：1995-06-08

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： G11C11/419 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C17/18 ,  G11L13/00

CPC分类号： G11C16/28

摘要： A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCC.sub.max. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

摘要翻译： 用于读取EPROM和ROM型存储单元的感测电路采用电路来产生在瞬变期间不受误差的偏移电流，从而允许实现减少的存取时间。 另一方面，感测电路保持电流偏移感测架构的固有优点，其由朝向最大值VCCmax的基本无限的工作电压范围表示。 电流产生电路通过补充的单元行驱动，每行读数被解码，并且在瞬变期间复制为读取选择的行的行为。

公开(公告)号：US5515332A

公开(公告)日：1996-05-07

申请号：US391160

申请日：1995-02-21

申请人： Luigi Pascucci ,  Marco Maccarrone ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Maccarrone ,  Marco Olivo

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32

CPC分类号： G11C7/02 ,  G11C16/32 ,  G11C7/1006 ,  G11C7/22

摘要： A load timing circuit including an output simulation circuit similar to the output circuits of the memory, so as to present the same propagation delay; a simulating signal source for generating a data simulating signal; a synchronizing network for detecting a predetermined switching edge of the data simulating signal and enabling supply of the signal to the output simulation circuit and data supply to the output circuits of the memory; a combinatorial network for detecting propagation of the data simulating signal to the output of the output simulation circuit and disabling the data simulating signal; and a reset element for resetting the timing circuit.

摘要翻译： 一种负载定时电路，包括与存储器的输出电路相似的输出模拟电路，以便呈现相同的传播延迟; 用于产生数据模拟信号的模拟信号源; 同步网络，用于检测数据模拟信号的预定切换边沿，并且能够向输出模拟电路提供信号，并向存储器的输出电路提供数据; 组合网络，用于检测数据模拟信号的传播到输出模拟电路的输出，并禁用数据模拟信号; 以及用于复位定时电路的复位元件。

公开(公告)号：US5469389A

公开(公告)日：1995-11-21

申请号：US219204

申请日：1994-03-29

申请人： Marco Olivo ,  Luigi Pascucci

发明人： Marco Olivo ,  Luigi Pascucci

IPC分类号： G11C29/00 ,  G11C11/00 ,  G11C29/04

CPC分类号： G11C11/00

摘要： There is described a semiconductor memory including a matrix of rows and columns of memory cells, wherein the columns are grouped together in sectors, each sector representing the portion of the matrix itself related to a data input/output line. Each sector is in turn divided into packets of columns, and there are redundancy columns suitable for replacing a matrix column containing defective memory cells. Each of the redundancy columns is included in a respective packet. The memory also includes control circuits to execute the abovementioned replacement.

摘要翻译： 描述了包括存储器单元的行和列的矩阵的半导体存储器，其中列被分组在扇区中，每个扇区表示矩阵本身与数据输入/输出线相关的部分。 每个扇区又被分成列的分组，并且存在适于替换包含有缺陷的存储单元的矩阵列的冗余列。 每个冗余列被包括在相应的分组中。 存储器还包括执行上述替换的控制电路。

公开(公告)号：US5844851A

公开(公告)日：1998-12-01

申请号：US412553

申请日：1995-03-29

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  G11C13/00

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/14 ,  G11C7/22

摘要： Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by simplifying the sensing process.

公开(公告)号：US5404334A

公开(公告)日：1995-04-04

申请号：US901862

申请日：1992-06-22

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  G11C13/00

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/14 ,  G11C7/22

摘要： Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by simplifying the sensing process.

摘要翻译： 通过允许输出锁存器通过具有预先建立的持续时间的使能脉冲允许输出锁存器改变新提取的数据信号的状态来防止可能由快速并行存储器件的输出缓冲器中的转变引起的噪声引起的杂散存储器读数， 仅在存储器地址信号的改变已经发生并且存储器地址信号的新配置持续了不短于通过存储器链的信号的传播时间的时间之后才产生。 使能脉冲通过采用在存储器的输入电路，虚拟存储器链，单触发脉冲发生器和复位脉冲发生器中发生的转换的检测器来产生。 也可以利用抗噪声网络来实现每个读取周期结束时的自动待机状态，从而通过简化感测过程来降低功耗并提高速度。