公开(公告)号：US20120218002A1

公开(公告)日：2012-08-30

申请号：US13446946

申请日：2012-04-13

Applicant: Kallol Chatterjee ,  Anurag Tiwari

Inventor： Kallol Chatterjee ,  Anurag Tiwari

IPC: G01R29/02

CPC classification number: G01R31/31709

Abstract: An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract translation: 一种用于测量时钟信号的两个边缘之间的时间间隔的装置，包括边缘发生器，第一多抽头延迟模块，第二多抽头延迟模块和多元件相位检测器。 边缘发生器在第一输出节点处产生第一边缘，并在第二输出节点处产生第二选择边缘。 第一多抽头延迟模块在每个抽头处向第一边缘提供第一增量延迟。 第二多抽头延迟模块在第二选择边缘的每个抽头处提供第二增量延迟。 多元件相位检测器的每个元件具有第一和第二输入端子。 第一输入端耦合到第一多抽头延迟模块的选定抽头，第二输入端耦合到第二多抽头延迟模块的对应抽头。 多元件相位检测器的输出端提供时间间隔的值。

公开(公告)号：US20120170587A1

公开(公告)日：2012-07-05

申请号：US12983116

申请日：2010-12-31

Applicant: Gaurav MATHUR ,  Pratik DAMLE

Inventor： Gaurav MATHUR ,  Pratik DAMLE

IPC: H04L12/56

CPC classification number: G06F13/4291 ,  G06F13/38 ,  G06F13/4022

Abstract: A circuit comprising: a device determiner configured to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line and at least one signal line; and a device router configured to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal.

Abstract translation: 一种电路，包括：设备确定器，被配置为在第一操作模式中，经由至少一个控制线和至少一个信号线中的至少一个接收设备选择信号; 以及设备路由器，被配置为在第二操作模式中，在至少一个控制线路与至少一个信号线路之间的至少一个和至少一个取决于所述设备选择信号的设备之间路由信号。

公开(公告)号：US20120170391A1

公开(公告)日：2012-07-05

申请号：US12981031

申请日：2010-12-29

Applicant: Dhori Kedar Janardan ,  Rakesh Kumar Sinha ,  Sachin Gulyani

Inventor： Dhori Kedar Janardan ,  Rakesh Kumar Sinha ,  Sachin Gulyani

IPC: G11C7/00

CPC classification number: G11C7/1096 ,  G11C5/147 ,  G11C7/04 ,  G11C11/413

Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.

Abstract translation: 存储电路包括被配置为可重写的存储单元。 写入使能电路被配置为使得能够根据写入信号经由一对位线将信号写入存储器单元。 电荷供给电路被配置为向所述一对位线中的至少一个提供电荷。 电荷供给控制器被配置为控制充电电路根据存储电路的温度和存储电路的电位差供给中的至少一个来提供电荷。

公开(公告)号：US20120169378A1

公开(公告)日：2012-07-05

申请号：US13118858

申请日：2011-05-31

Applicant: Prashant Dubey ,  Navneet Gupta ,  Shailesh Kumar Pathak ,  Kaushik Saha ,  Gagandeep Singh Sachdev

Inventor： Prashant Dubey ,  Navneet Gupta ,  Shailesh Kumar Pathak ,  Kaushik Saha ,  Gagandeep Singh Sachdev

IPC: G01R19/00 ,  H03K5/00

CPC classification number: G11C7/065 ,  H04L25/0274

Abstract: A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Abstract translation: 第一感测电路具有耦合到真实差分信号线和互补差分信号线的输入端。 第二感测电路还具有耦合到所述真实信号和所述互补信号的输入端子。 每个感测电路具有真实的信号感测路径和互补信号感测路径。 第一感测电路具有偏置于互补信号感测路径的不平衡，而第二感测电路具有被偏置到真实信号感测路径的不平衡。 来自第一和第二感测电路的输出由逻辑电路处理，该逻辑电路产生一个输出信号，该输出信号指示在真实差分信号线和互补差分信号线之间是否存在足够的用于感测的差分信号。

公开(公告)号：US20120166900A1

公开(公告)日：2012-06-28

申请号：US13162784

申请日：2011-06-17

Applicant: Ajay Kumar Dimri

Inventor： Ajay Kumar Dimri

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318541

Abstract: A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is configured such that a fault with the first circuit and said second circuit is determined in dependence on an output of the first circuit.

Abstract translation: 第一电路具有复位输入。 第二电路被配置为复位并提供输出。 测试电路被配置为测试第一电路和第二电路。 测试电路被配置为使得根据第一电路的输出来确定与第一电路和所述第二电路的故障。

公开(公告)号：US20120166856A1

公开(公告)日：2012-06-28

申请号：US13172647

申请日：2011-06-29

Applicant: Ankur BAL ,  Anupam JAIN

Inventor： Ankur BAL ,  Anupam JAIN

IPC: G06F1/12

CPC classification number: H03K5/135 ,  G06F1/12 ,  H04L7/0045 ,  H04L7/02

Abstract: Signal synchronizing systems and methods are disclosed. A signal synchronizing system includes a sequential logic circuit to receive an input signal and to generate a plurality of intermediate signals from the input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. A signal receiver includes a microcontroller and a signal synchronizer coupled to the microcontroller. The signal synchronizer includes a sequential logic circuit to receive an input signal from a transmitter and to generate a plurality of intermediate signals from the received input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal.

Abstract translation: 公开了信号同步系统和方法。 信号同步系统包括顺序逻辑电路，用于接收输入信号并根据时钟信号从输入信号产生多个中间信号。 逻辑电路组合中间信号以产生输出信号。 信号接收机包括耦合到微控制器的微控制器和信号同步器。 信号同步器包括顺序逻辑电路，用于接收来自发射机的输入信号，并且基于时钟信号从所接收的输入信号产生多个中间信号。 逻辑电路组合中间信号以产生输出信号。

公开(公告)号：US20120163064A1

公开(公告)日：2012-06-28

申请号：US13178856

申请日：2011-07-08

Applicant: Nitin Jain ,  Piyush Jain

Inventor： Nitin Jain ,  Piyush Jain

IPC: G11C17/08 ,  G11C17/00

CPC classification number: G11C17/12 ,  G11C11/5692 ,  G11C2207/002

Abstract: A read only memory cell circuit is provided. The memory cell circuit includes at least one memory cell. A pair of bit lines associated with each memory cell is provided which form a complementary output. The at least one memory cell is configured to be coupled to first or second of the bit line pair.

Abstract translation: 提供只读存储单元电路。 存储单元电路包括至少一个存储单元。 提供与每个存储器单元相关联的一对位线，其形成互补输出。 至少一个存储器单元被配置为耦合到位线对的第一或第二。

公开(公告)号：US20120163063A1

公开(公告)日：2012-06-28

申请号：US13168609

申请日：2011-06-24

Applicant: Jitendra DASANI

Inventor： Jitendra DASANI

IPC: G11C17/08 ,  H01L21/8246

CPC classification number: G11C17/08 ,  G11C7/065 ,  G11C17/12 ,  H01L27/11226

Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Abstract translation: 互补型只读存储器（ROM）单元包括晶体管; 以及与晶体管相邻的位线和互补位线; 其中所述晶体管的漏极端子基于所述ROM单元中编程的数据连接到所述位线和所述互补位线之一。

公开(公告)号：US20120102538A1

公开(公告)日：2012-04-26

申请号：US12910432

申请日：2010-10-22

Applicant: Rahul Bansal ,  Philippe Monnier ,  Shiv Kumar Singh ,  Kausik Maiti ,  Nitin Jain

Inventor： Rahul Bansal ,  Philippe Monnier ,  Shiv Kumar Singh ,  Kausik Maiti ,  Nitin Jain

IPC: G10L19/00 ,  H04N7/16

CPC classification number: H04N21/4341 ,  G10L19/16 ,  H04N21/4344 ,  H04N21/8106

Abstract: An embodiment of the present invention discloses a system and method for decoding multiple independent encoded audio streams using a single decoder. The system includes one or more parsers, a preprocessor, an audio decoder, and a renderer. The parser extracts individual audio frames from each input audio stream. The preprocessor combines the outputs of all parsers into a single audio frame stream and enables sharing of the audio decoder among multiple independent encoded audio streams. The audio decoder decodes the single audio frame stream and provides a single decoded audio stream. And the renderer renders the individual reconstructed audio streams from the single decoded audio stream.

Abstract translation: 本发明的实施例公开了一种使用单个解码器解码多个独立编码音频流的系统和方法。 系统包括一个或多个解析器，预处理器，音频解码器和渲染器。 解析器从每个输入音频流中提取单个音频帧。 预处理器将所有解析器的输出组合成单个音频帧流，并使多个独立编码音频流之间的音频解码器共享。 音频解码器解码单个音频帧流，并提供单个解码的音频流。 并且渲染器从单个解码的音频流渲染单独的重构音频流。

公开(公告)号：US08130579B2

公开(公告)日：2012-03-06

申请号：US12717019

申请日：2010-03-03

Applicant: Ashish Kumar ,  Piyush Jain

Inventor： Ashish Kumar ,  Piyush Jain

IPC: G11C7/00

CPC classification number: G11C11/412

Abstract: Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a memory cell can be lowered and an electric potential of a lower power supply node of the memory cell can be raised before writing data to the memory cell.

Abstract translation: 公开了存储器件和操作存储单元的方法，其中位线可以在与电浮动接地线电荷共享之后并且在将数据写入存储器单元之前接地。 可以降低存储单元的上电源节点的电位，并且可以在将数据写入存储单元之前提升存储单元的下电源节点的电位。