公开(公告)号：US4752902A

公开(公告)日：1988-06-21

申请号：US752823

申请日：1985-07-08

Applicant: Bar-Giora Goldberg

Inventor： Bar-Giora Goldberg

IPC: G06F1/03 ,  H03B19/00

CPC classification number: G06F1/0328

Abstract: N stages of BCD adders receive as a first addend BCD encoded information representing a desired frequency. They receive as a second addend the outputs of N stages of four-bit registers. The summing outputs of the adders are input data for the registers. The data is clocked into the register by a stable frequency source. The outputs from a plurality of the most significant stages of the registers are used to address a ROM. Using the periodically changing BCD address, a sinusoidal function is retrieved in individual samples from the ROM. Digital data from the ROM is converted to analog. A low pass filter enhances the desired frequency and suitably attenuates higher frequencies. An equalizer compensates for power roll-off.

Abstract translation: B级加法器的N级作为代表期望频率的第一加数BCD编码信息而接收。 它们作为第二个加法来接收N位四位寄存器的输出。 加法器的求和输出是寄存器的输入数据。 数据由稳定的频率源输入寄存器。 来自寄存器的多个最高有效级的输出用于寻址ROM。 使用周期性变化的BCD地址，从ROM中的各个采样中检索正弦函数。 来自ROM的数字数据被转换为模拟数据。 低通滤波器增强了所需的频率并适当地衰减较高的频率。 均衡器补偿电力滚降。

公开(公告)号：US3610806A

公开(公告)日：1971-10-05

申请号：US3610806D

申请日：1969-10-30

Applicant: NORTH AMERICAN ROCKWELL

Inventor： DEUTSCH RALPH

IPC: G06F1/02 ,  G06F1/03 ,  G10H1/057 ,  G10H1/18 ,  G10H1/20 ,  G10H7/04 ,  G10H1/02

CPC classification number: G10H7/04 ,  G06F1/02 ,  G06F1/0328 ,  G10H1/0575 ,  G10H1/182 ,  G10H1/20

Abstract: In an electronic organ the actuation of keys in accordance with corresponding audible tones to be reproduced effects the gating of pulses into time slots of a time division multiplexed signal, the time slots of the multiplexed signal being structured in accordance with a desired assignment sequence to correspond to the keys and to be representative thereof for identifying each note capable of being generated by the organ. A set of note, or tone, generators with availability assignment control means for capturing a pulse in the multiplexed signal are each rendered responsive to a given captured pulse for generating the tone represented by that pulse. The appropriate tone is generated digitally in the form of amplitude samples of a waveform stored in a memory, and the amplitude samples are subsequently subjected to digital-to-analog conversion for ultimate production of the audible output of the organ. Attack and decay of the tone waveform envelope are simulated by appropriately scaling the amplitude samples at the leading and trailing portions of the waveform envelope. An adaptive sustain operating mode is provided by which the length of decay is varied according to the availability of tone generators where the number of tone generators is limited.

公开(公告)号：US3610799A

公开(公告)日：1971-10-05

申请号：US3610799D

申请日：1969-10-30

Applicant: NORTH AMERICAN ROCKWELL

Inventor： WATSON GEORGE A

IPC: G06F1/02 ,  G06F1/03 ,  G10H1/057 ,  G10H1/18 ,  G10H1/20 ,  G10H7/04 ,  G10H1/00

CPC classification number: G10H7/04 ,  G06F1/02 ,  G06F1/0328 ,  G10H1/0575 ,  G10H1/182 ,  G10H1/20

Abstract: In an electric organ, the actuation of keys in accordance with corresponding, audible tones to be reproduced effects the gating of pulses into time slots of a time division multiplex signal, the time slots of the multiplex signal being structured in accordance with a desired assignment sequence to correspond to the keys and to be representative thereof for identifying each note capable of being generated by the organ. A set of note, or tone, generators with availability assignment control means for capturing a pulse in the multiplex signal are each rendered responsive to a given captured pulse for generating the tone represented by that pulse. A second multiplex system having time slot pulse assignments additionally provides for generation of a time division multiplex signal for control of voices and other characteristics to be imparted to the reproduced tones.

Abstract translation: 存储器包含由相应地址识别的多个离散位置中的相关信息内容的数字数据。 存储器以取决于从存储器顺序读取的来自各个位置的数据之间的期望间隔的速率被寻址或访问。 在具体实施例中，数据构成乐器产生的类型的复波形的振幅值，沿着波形的轴线等间隔的时间点。 用于以多个选择性控制速率中的任何一个寻址存储器的装置包括用于连续地计算每组数量的数字的计算器，每个数字在存储器读出期间定义数据之间的不同间隔。 当选择期望的读出速率时，如通过选择所存储的波形的完整周期的期望重复频率，与该速率相关联的数量从计算的集合中被采样并且周期性地增加其自身的值以识别适当的数据 存储器中的地址，用于以对应于期望的读出速率的周期性增加的间隔访问该数据。

公开(公告)号：US20240210985A1

公开(公告)日：2024-06-27

申请号：US18543676

申请日：2023-12-18

Applicant: Rohde & Schwarz GmbH & Co. KG

Inventor： Julius SEEGER

IPC: G06F1/03 ,  G01R31/28 ,  G06F1/02 ,  G06F1/08

CPC classification number: G06F1/0328 ,  G01R31/2841 ,  G06F1/022 ,  G06F1/08

Abstract: A DDS circuit includes a phase accumulator circuit. The phase accumulator circuit includes a clock input being configured to receive a clock signal. The phase accumulator circuit includes a frequency tuning register configured to receive a frequency tuning word (FTW), and a phase shift register configured to receive a phase shift word (PSW). The phase accumulator circuit also includes a phase increment sub-circuit configured to increment a phase signal output by the phase accumulator circuit by a predetermined phase increment based on the clock signal and/or based on the FTW. The phase accumulator circuit further includes a feedback path configured to feed back the phase signal to the phase increment sub-circuit. The phase accumulator circuit further includes a phase correction sub-circuit configured to adapt the phase signal fed back to the phase increment sub-circuit based on the phase shift word.

公开(公告)号：US09861822B2

公开(公告)日：2018-01-09

申请号：US14446996

申请日：2014-07-30

Applicant: Nuvectra Corporation

Inventor： Stephen C. Trier ,  Jeffrey A. Weisgarber ,  Richard J. Polefko

IPC: A61N1/00 ,  A61N1/36 ,  G06F1/03 ,  A61N1/362 ,  A61N1/372

CPC classification number: A61N1/36146 ,  A61N1/36071 ,  A61N1/36125 ,  A61N1/3615 ,  A61N1/36167 ,  A61N1/36175 ,  A61N1/3625 ,  A61N1/37235 ,  G06F1/0328

Abstract: A method, device and/or system for generating arbitrary waveforms of a desired shape that can be used for generating a stimulation pulse for medical purposes such as for spinal cord stimulation therapy.

公开(公告)号：US09772972B2

公开(公告)日：2017-09-26

申请号：US15205817

申请日：2016-07-08

Applicant: Syntropy Systems, LLC

Inventor： Christopher Pagnanelli

IPC: G06F1/04 ,  G06F1/02 ,  G06F1/03 ,  G06F17/14 ,  H03H17/04

CPC classification number: G06F17/147 ,  G06F1/022 ,  G06F1/0328 ,  G06F1/04 ,  H03H17/04

Abstract: Provided are, among other things, systems, apparatuses methods and techniques for generating discrete-time sinusoidal sequences. One such apparatus includes a plurality of parallel processing branches, with each of the parallel processing branches operating at a subsampled rate and utilizing a recursive filter to generate sub-rate samples which represent a different subsampling phase of a complete signal that is output by the apparatus.

公开(公告)号：US09547327B2

公开(公告)日：2017-01-17

申请号：US15006088

申请日：2016-01-25

Applicant: Pentomics, Inc.

Inventor： Alan N. Willson, Jr. ,  Tianyu Hu ,  Yunfan Liu

IPC: G06F5/01 ,  G06F1/02 ,  G06F1/03 ,  G06F1/035 ,  G06F7/00

CPC classification number: G06F1/022 ,  G06F1/03 ,  G06F1/0328 ,  G06F1/035 ,  G06F5/01 ,  G06F7/00

Abstract: Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided. Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to be responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time.

Abstract translation: 提供了具有多个子相位累加器的分相相位累加器的系统和方法。 每个子相位累加器接收频率控制字的一部分。 第一子相位累加器包括第一寄存器，其余子相位累加器包括寄存器和溢出寄存器。 在每个离散时间点，第一子相位累加器被配置为响应于该离散时间点处的频率控制字的第一部分以及在紧接的先前离散时间点处的第一子相位累加器值，以及 每个剩余的子相位累加器被配置为响应于在该离散时间点处的频率控制字的对应部分的值以及在紧接的先前离散时间点处的相同的第二子相位累加器值。

公开(公告)号：US20160147251A1

公开(公告)日：2016-05-26

申请号：US14901163

申请日：2014-06-02

Applicant: ENDRESS+HAUSER GMBH+CO. KG

Inventor： Stefan Rummele-Werner ,  Dietmar Fruhauf ,  Armin Wernet ,  Kaj Uppenkamp ,  Gerd Bechtel

IPC: G06F1/08

CPC classification number: G06F1/08 ,  G01F23/266 ,  G06F1/0321 ,  G06F1/0328

Abstract: The invention relates to a signal generator for producing periodic signals for a measuring apparatus (1) of automation technology, wherein the signals have sequential, discrete signal frequencies, which lie within a predetermined frequency range, a control- and/or computing unit (4), a clock signal producer (6), wherein the clock signal producer (6) provides a constant sampling frequency, which is greater than the maximum discrete signal frequency in the predetermined frequency range, a memory unit (7), in which for each of the discrete signal frequencies the amplitude values of the corresponding periodic signals are stored or storable as a function of the sampling frequency, wherein the control- and/or computing unit (4) reads out the stored or storable amplitude values of the discrete frequencies successively with the sampling frequency of the clock (6) from the memory unit (7) and produces the periodic signals or forwards for producing, and a static filter unit (12) with a limit frequency, which lies above the maximum signal frequency and which removes frequency fractions caused by the sampling.

Abstract translation: 本发明涉及一种用于生成自动化技术的测量装置（1）的周期信号的信号发生器，其中信号具有位于预定频率范围内的顺序的离散信号频率，控制和/或计算单元（4） ），时钟信号发生器（6），其中所述时钟信号发生器（6）提供大于所述预定频率范围内的最大离散信号频率的恒定采样频率;存储器单元（7），其中对于每个 离散信号频率的相应周期信号的振幅值作为采样频率的函数被存储或存储，其中控制和/或计算单元（4）连续地读出离散频率的存储或存储幅度值 具有来自存储器单元（7）的时钟（6）的采样频率并产生周期性信号或向前产生，以及具有限制频率的静态滤波器单元（12） 该位置高于最大信号频率，并且消除了由采样引起的频率分数。

公开(公告)号：US09244483B1

公开(公告)日：2016-01-26

申请号：US13205525

申请日：2011-08-08

Applicant: Alan N. Willson, Jr.

Inventor： Alan N. Willson, Jr.

IPC: G06F1/03 ,  G06F1/035

CPC classification number: G06F1/0328 ,  G06F1/03 ,  G06F1/035

Abstract: Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided, Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to be responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time.

Abstract translation: 提供了具有多个子相位累加器的分相相位累加器的系统和方法，每个子相位累加器接收频率控制字的一部分。 第一子相位累加器包括第一寄存器，其余子相位累加器包括寄存器和溢出寄存器。 在每个离散时间点，第一子相位累加器被配置为响应于该离散时间点处的频率控制字的第一部分以及在紧接的先前离散时间点处的第一子相位累加器值，以及 每个剩余的子相位累加器被配置为响应于在该离散时间点处的频率控制字的对应部分的值以及在紧接的先前离散时间点处的相同的第二子相位累加器值。

公开(公告)号：US09021002B2

公开(公告)日：2015-04-28

申请号：US13760012

申请日：2013-02-05

Applicant: Hong Kong Applied Science & Technology Research Institute Company Limited

Inventor： Zhongzi Chen ,  Beiping Yan ,  Xiao Huo ,  Xiaowu Cai

IPC: G06F1/02 ,  G06F1/03

CPC classification number: G06F1/0321 ,  G06F1/0328 ,  G06F1/0353 ,  G06F1/0356

Abstract: A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.

Abstract translation: 直接数字合成器（DDS）的正弦波发生器将数字相位输入转换为数字正弦波输出。 正弦值和斜率存储在只读存储器（ROM）中用于第一象限中的粗略高位相位。 象限文件夹和分相器反映和反转第一象限的值，以产生所有四个象限的幅度。 每个正弦值和斜率都存储在较低相位位的范围内。 一个Delta位分离高位和低位相位。 Delta有条件地反转低位相位，正弦值和最终极性。 减少的AND逻辑阵列将斜率乘以有条件反相的下相位位。 然后，重建的ADD逻辑阵列会添加有条件反转的正弦值。 添加有条件反转的极性以产生最终正弦值。 基于Delta位的条件反演精简生成逻辑。