公开(公告)号：US10977192B1

公开(公告)日：2021-04-13

申请号：US15094656

申请日：2016-04-08

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Nafea Bshara

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/10

Abstract: Disclosed herein is an apparatus configured to log transactions of a translation lookaside buffer (TLB) into a software-accessible buffer. The apparatus includes a memory management unit (MMU) configured to translate a logical memory address to a physical memory address for accessing a physical memory. The apparatus also includes a TLB configured to store a plurality of entries, where each entry includes a logical memory page address and an associated physical memory page address. The apparatus further includes a software-accessible buffer and a TLB event logging circuit configured to detect an event associated with an entry of the TLB and store information regarding the detected event in the software-accessible buffer.

公开(公告)号：US10976931B2

公开(公告)日：2021-04-13

申请号：US16576014

申请日：2019-09-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael K. Gschwind ,  Valentina Salapura

IPC: G06F12/10 ,  G06F3/06 ,  G06F12/1009 ,  G06F12/0891 ,  G06F12/126 ,  G06F12/109 ,  G06F12/1036 ,  G06F12/14

Abstract: A determination is made that a unit of memory that provides storage for one or more in-memory configuration state registers is to be pinned in a system that includes a guest operating system and one or more hosts at one or more host levels. Based on determining that the unit of memory is to be pinned, at least one host of the one or more hosts is notified that the unit of memory is to be pinned.

公开(公告)号：US10915456B2

公开(公告)日：2021-02-09

申请号：US16417961

申请日：2019-05-21

Applicant: International Business Machines Corporation

Inventor： Debapriya Chatterjee ,  Bryant Cockcroft ,  Larry Leitner ,  John A. Schumann ,  Karen Yokum

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/109 ,  G06F12/1036

Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.

公开(公告)号：US20200301851A1

公开(公告)日：2020-09-24

申请号：US16414768

申请日：2019-05-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Che-Yueh Kuo ,  Ding-Yuan Chen

IPC: G06F12/1036 ,  G06F12/02 ,  G06F12/12

Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: maintaining first management information for identifying a first management unit in the rewritable non-volatile memory module; collecting first valid data from the first management unit according to the first management information without reading first mapping information from the rewritable non-volatile memory module in a data merge operation, and the first mapping information includes logical-to-physical mapping information related to the first valid data; and storing the collected first valid data into a recycling unit.

公开(公告)号：US20200272576A1

公开(公告)日：2020-08-27

申请号：US16800913

申请日：2020-02-25

Applicant: Marvell Asia Pte Ltd.

Inventor： Avi Haimzon ,  Adi Katz

IPC: G06F12/1009 ,  G06F12/1036 ,  G06F12/02 ,  G06F9/30 ,  G06F13/16

Abstract: A first master receives a first virtual address in a virtual memory, the first virtual address in the virtual memory corresponding, according to a mapping function, to a first physical address of a first physical memory bank which is to be accessed by the first master. The first master accesses the first physical address to perform a first memory operation in the first memory bank. A second master receives a second virtual address in a virtual memory, the second virtual address in the virtual memory corresponding, according to the mapping function, to a second physical address of a second physical memory bank which is to be accessed by the second master. Concurrently with access by the first master to the first physical address, the second master accesses the second physical address to perform a second memory operation in the second physical memory bank.

公开(公告)号：US10740248B2

公开(公告)日：2020-08-11

申请号：US16218903

申请日：2018-12-13

Applicant: International Business Machines Corporation

Inventor： David Campbell ,  Dwain A. Hicks ,  Christian Jacobi

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/1018 ,  G06F12/0862 ,  G06F9/38 ,  G06F12/123

Abstract: A method or system of translating a virtualized address to a real address is disclosed that includes receiving a virtualized address for translation; generating a predicted intermediate address translation using a portion of the bit field of the virtualized address; determining a predicted real address using the predicted intermediate address or portion thereof; performing a translation of the virtualized address to an actual intermediate address; determining whether the predicted intermediate address is the same as the actual intermediate address; and in response to the predicted intermediate address being the same as the actual intermediate address, providing the predicted real address as the real address.

公开(公告)号：US10705976B2

公开(公告)日：2020-07-07

申请号：US16023537

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Ravi Sahita ,  Barry E. Huntley ,  Vedvyas Shanbhogue ,  Dror Caspi ,  Baruch Chaikin ,  Gilbert Neiger ,  Arie Aharon ,  Arumugam Thiyagarajah

IPC: G06F12/1036 ,  G06F12/14 ,  G06F9/455 ,  G06F12/109 ,  G06F21/53 ,  G06F21/78 ,  G06F12/1009 ,  G06F12/02

Abstract: Examples include a processor including at least one untrusted extended page table (EPT), circuitry to execute a set of instructions of the instruction set architecture (ISA) of the processor to manage at least one secure extended page table (SEPT), and a physical address translation component to translate a guest physical address of a guest physical memory to a host physical address of a host physical memory using one of the at least one untrusted EPT and the at least one SEPT.

公开(公告)号：US20200151111A1

公开(公告)日：2020-05-14

申请号：US16745019

申请日：2020-01-16

Applicant: ARM Limited

Inventor： Steven Douglas KRUEGER

IPC: G06F12/1045 ,  G06F12/12 ,  G06F12/0891 ,  G06F12/0875 ,  G06F12/1036 ,  G06F12/0842 ,  G06F12/084 ,  G06F12/1027 ,  G06F12/126 ,  G06F12/109

Abstract: A request for data from a cache (TLB or data/instruction cache) specifies a partition identifier allocated to a software execution environment associated with the request. Allocation of data to the cache is controlled based on a set of configuration information selected based on the partition identifier specified by the request. For a TLB, this allows different allocation policies to be used for requests associated with different software execution environments. In one example, the cache allocation is controlled based on an allocation threshold specified by the selected set of configuration information, which limits the maximum number of cache entries allowed to be allocated with data associated with the corresponding partition identifier.

公开(公告)号：US10649911B2

公开(公告)日：2020-05-12

申请号：US15940490

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Hormuzd M. Khosravi ,  Baiju Patel ,  Ravi Sahita ,  Barry Huntley

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/0891 ,  G06F21/79 ,  G06F21/62

Abstract: Embodiment of this disclosure provide techniques to support full memory paging between different trust domains (TDs) in compute system without losing any of the security properties, such as tamper resistant/detection and confidentiality, on a per TD basis. In one embodiment, a processing device including a memory controller and a memory paging circuit operatively coupled to the memory controller is provided. The memory paging circuit is to evict a memory page associated with a trust domain (TD) executed by the processing device. A binding of the memory page to a first memory location of the TD is removed. A transportable page that includes encrypted contents of the memory page is created. Thereupon, the memory page is provided to a second memory location.

公开(公告)号：US10545671B1

公开(公告)日：2020-01-28

申请号：US15664174

申请日：2017-07-31

Applicant: EMC IP Holding Company, LLC

Inventor： Xiaohua Fan ,  Yaming Kuang ,  Walter Forrester

IPC: G06F9/355 ,  G06F3/06 ,  G06F12/1036 ,  G06F12/02

Abstract: A method, computer program product, and computer system for receiving, at a computing device, an I/O request directed to a compressed data portion of a storage system. It may be determined whether the I/O request includes one of a first portion of information and a second portion of information. An address of the compressed data portion may be obtained via downward mapping if the I/O request includes the first portion of information. The address of the compressed data portion may be obtained via upward mapping if the I/O request includes the second portion of information. The I/O request may be executed at the compressed data portion.