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公开(公告)号：US20230018356A1
公开(公告)日：2023-01-19
申请号：US17812062
申请日：2022-07-12
Inventor： Hugo Gicquel , Sandrine Nicolas , Cedric Rechatin , Reiner Welk
IPC: H03F3/193
Abstract: In an embodiment an amplifier includes a first MOS transistor having a drain connected to an output of the amplifier and a source coupled to a first node configured to receive a first power supply potential, a first capacitive element connected between an input of the amplifier and a gate of the first MOS transistor, a first current source connecting the drain of the first MOS transistor to a second node configured to receive a second power supply potential and a resistive element and a second capacitive element connected in parallel between the gate and the drain of the first MOS transistor, the resistive element including a switched capacitor.
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公开(公告)号：US11533019B2
公开(公告)日：2022-12-20
申请号：US17180752
申请日：2021-02-20
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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123.发明授权公开(公告)号：US11522360B2
公开(公告)日：2022-12-06
申请号：US17202566
申请日：2021-03-16
Applicant: STMicroelectronics (Alps) SAS
Inventor： Frederic Lebon , Laurent Chevalier
Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.
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公开(公告)号：US11469671B2
公开(公告)日：2022-10-11
申请号：US17324782
申请日：2021-05-19
Applicant: STMicroelectronics (Alps) SAS
Inventor： Thomas Jouanneau
Abstract: The integrated circuit includes a first node intended to be biased at a first voltage, a second node intended to be biased at a second voltage and having a non-negligible capacitive coupling with the first node. A power supply management device comprises a voltage booster configured to boost a power supply voltage and comprising boost stages configured to generate intermediate voltages on intermediate nodes. A compatibility detection circuit is configured to detect compatibility between the second voltage and one of the intermediate voltages, and, if the second voltage is compatible with an intermediate voltage, to couple the at least one second node to the compatible intermediate node.
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公开(公告)号：US20220318392A1
公开(公告)日：2022-10-06
申请号：US17657027
申请日：2022-03-29
Inventor： Franck Albesa , Nicolas Anquet
IPC: G06F21/57 , G06F21/60 , G06F9/4401
Abstract: The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.
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Patent Agency Ranking
公开(公告)号：US20220198005A1
公开(公告)日：2022-06-23
申请号：US17644711
申请日：2021-12-16
Inventor： Diana Moisuc , Christophe Eichwald
Abstract: Method for detecting the linear extraction of information in a processor using an instruction pointer. The method includes monitoring the values of the instruction pointer, determining a number of consecutive increments incrementing the values of the instruction pointer by a constant amount, and generating a detection signal if the number is greater than or equal to a detection threshold.
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公开(公告)号：US20220180004A1
公开(公告)日：2022-06-09
申请号：US17544038
申请日：2021-12-07
Applicant: STMICROELECTRONICS SA , STMicroelectronics (Alps) SAS
Inventor： Julien Goulier , Pascal Bernon
Abstract: The present description concerns an integrated circuit including, between first and second terminals having a first voltage applied therebetween, a load configured to execute instructions, a circuit for delivering a digital signal having at least two bits from a binary signal and a current output digital-to-analog converter controlled by the digital signal and coupled between the first and second terminals in parallel with the load.
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公开(公告)号：US11353905B2
公开(公告)日：2022-06-07
申请号：US16787679
申请日：2020-02-11
Inventor： Jean Camiolo , Alexandre Pons
IPC: G05F1/575 , G01R19/165 , G05F3/18 , G06F1/26 , H03F3/45 , H03K3/0233 , G05F1/56
Abstract: A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.
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公开(公告)号：US11283353B2
公开(公告)日：2022-03-22
申请号：US16385284
申请日：2019-04-16
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Francois Druilhe , Patrik Arno , Alessandro Inglese , Michele Alessandro Carrano
Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
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公开(公告)号：US20220028844A1
公开(公告)日：2022-01-27
申请号：US17374868
申请日：2021-07-13
Inventor： Deborah COGONI , David AUCHERE , Laurent SCHWARTZ , Claire Laporte
Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.
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